arch-arm: Inital vector rename mode depending on A32/A64

Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Reviewed-on: https://gem5-review.googlesource.com/c/15599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 52c42cb9562d5450cc8008a44d6dec9424a4425b..b4e8536a0d6d7eeaa7f0ce6683ba45ab4c156cea 100644 (file)
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -87,10 +87,6 @@ class ArmISA(SimObject):
     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
         "AArch64 Auxiliary Feature Register 1")
 
-    # Initial vector register rename mode
-    vecRegRenameMode = Param.VecRegRenameMode('Full',
-        "Initial rename mode for vecregs")
-
     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
         "AArch64 Debug Feature Register 0")

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6cbf8db9017f60d12e8c7a40aff8639d611c7d2c..97de97e6e50ed3ed84698590b9053baee8736a8a 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -62,7 +62,7 @@ ISA::ISA(Params *p)
     : SimObject(p),
       system(NULL),
       _decoderFlavour(p->decoderFlavour),
-      _vecRegRenameMode(p->vecRegRenameMode),
+      _vecRegRenameMode(Enums::Full),
       pmu(p->pmu),
       impdefAsNop(p->impdef_nop)
 {
@@ -103,6 +103,10 @@ ISA::ISA(Params *p)
         haveGICv3CPUInterface = true;
     }
 
+    // Initial rename mode depends on highestEL
+    const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
+        highestELIs64 ? Enums::Full : Enums::Elem;
+
     initializeMiscRegMetadata();
     preUnflattenMiscReg();