fix wishbone optional stall

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index 9d7d0d1f6e55ee3c2bf43da65d67fa53b0539c54..b6d522fbf5095ad54611f47ecc6649f16aab0a66 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -310,7 +310,7 @@ class TAP(Elaboratable):
                  manufacturer_id=Const(0b10001111111, 11),
                  part_number=Const(1, 16),
                  version=Const(0, 4),
-                 name=None, src_loc_at=0:
+                 name=None, src_loc_at=0):
         assert((ir_width is None) or (isinstance(ir_width, int) and
                ir_width >= 2))
         assert(len(version) == 4)
@@ -680,8 +680,11 @@ class TAP(Elaboratable):
                         m.d[domain] += wb.dat_w.eq(sr_data.o)
                         m.next = "WRITEREAD"
                 with m.State("READ"):
-                    with m.If(~wb.stall):
+                    if not hasattr(wb, "stall"):
                         m.next = "READACK"
+                    else:
+                        with m.If(~wb.stall):
+                            m.next = "READACK"
                 with m.State("READACK"):
                     with m.If(wb.ack):
                         # Store read data in sr_data.i
@@ -689,8 +692,11 @@ class TAP(Elaboratable):
                         m.d[domain] += sr_data.i.eq(wb.dat_r)
                         m.next = "IDLE"
                 with m.State("WRITEREAD"):
-                    with m.If(~wb.stall):
+                    if not hasattr(wb, "stall"):
                         m.next = "WRITEREADACK"
+                    else:
+                        with m.If(~wb.stall):
+                            m.next = "WRITEREADACK"
                 with m.State("WRITEREADACK"):
                     with m.If(wb.ack):
                         m.d[domain] += wb.adr.eq(wb.adr + 1)