i965/icl: Allow headerless sampler messages for pre-emptable contexts
authorAnuj Phogat <anuj.phogat@gmail.com>
Fri, 17 Aug 2018 23:36:17 +0000 (16:36 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Tue, 21 Aug 2018 19:50:05 +0000 (12:50 -0700)
It fixes simulator warnings in piglit tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_state_upload.c

index 855f1c7d7446c953a61001542d80e3abee389b87..433314115b121fe5e589870e082ac8b3ff897a1e 100644 (file)
@@ -1673,4 +1673,8 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GLK_SCEC_BARRIER_MODE_3D_HULL     (1 << 7)
 # define GLK_SCEC_BARRIER_MODE_MASK        REG_MASK(1 << 7)
 
+#define GEN11_SAMPLER_MODE                                  0xE18C
+# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS        (1 << 5)
+# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 5)
+
 #endif
index 757426407c375b21c057e6f054f086a2c516e480..2af4c45bc44eecf9d4b152bf7f96edfa8b7440fb 100644 (file)
@@ -63,6 +63,17 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
    brw_upload_invariant_state(brw);
 
+   if (devinfo->gen == 11) {
+      /* The default behavior of bit 5 "Headerless Message for Pre-emptable
+       * Contexts" in SAMPLER MODE register is set to 0, which means
+       * headerless sampler messages are not allowed for pre-emptable
+       * contexts. Set the bit 5 to 1 to allow them.
+       */
+      brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
+                              HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK |
+                              HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
+   }
+
    if (devinfo->gen == 10 || devinfo->gen == 11) {
       /* From gen10 workaround table in h/w specs:
        *