aiger: -xaiger to parse initial state back into (* init *) on Q wire

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7e5e6dd2daf5ef2dfeb560e23d84ec926646ea14..ed3a926c672ed0d386065432b9927ce4ef0001f0 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -802,7 +802,8 @@ void AigerReader::post_process()
                ff->setPort(ID::C, r.first->second);
                ff->setPort(ID::D, d);
                ff->setPort(ID::Q, q);
-               ff->attributes[ID::abc9_init] = initial_state[i];
+               log_assert(GetSize(q) == 1);
+               q->attributes[ID::init] = initial_state[i];
        }
 
        dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;