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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 72e9d9ec76c6d4fa2c648d7118376261f84aa93e..e3b44a38638ee8b5f589a839af7035a8982eaae6 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -78,8 +78,8 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
 | 6 | 7 | 19-20 |  21 | 22   23 |  description     |
 | - | - |-------| --- |---------|----------------- |
-| / |SNZ| 0 RG  |   0 | dz  sz  | simple mode                      |
-| / |SNZ| 0 RG  |   1 | dz  sz   | scalar reduce mode (mapreduce) |
+| / | / | 0 RG  |   0 | dz  sz  | simple mode                      |
+| / | / | 0 RG  |   1 | dz  sz  | scalar reduce mode (mapreduce) |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 | / |SNZ| 1 VLI | inv |  dz sz  | Ffirst 5-bit mode (implies CR-bit=EQ) |
 
@@ -87,8 +87,7 @@ Fields:
 
 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
 * **zz** set both sz and dz equal to this flag
-* **SNZ** when sz=1 and SNZ=1 a value "1" is put in place of zeros when
-  the predicate bit is clear (on both source and destination masks)
+* **SNZ** In fail-first mode, on the bit being tested, when sz=1 and SNZ=1 a value "1" is put in place of "0".
 * **inv CR-bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1