re PR target/48366 (ICE in extract_constrain_insn_cached, at recog.c:2024)

	PR target/48366
	* config/pa/pa.c (hppa_register_move_cost): Increase to 18 cost of
	move from floating point to shift amount register .
	(emit_move_sequence): Remove secondary reload support for floating
	point to shift amount amount register copies.
	(pa_secondary_reload): Return GENERAL_REGS for floating point/shift
	amount register copies.
	* config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
	register, return false if mode isn't a scalar integer mode.
	* config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.

From-SVN: r172197

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 619caebdc06097da8899cd676b5e3515a18e4519..719f8dd14bdc76547d0469d5ba88e457b9d67b25 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2011-04-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+       PR target/48366
+       * config/pa/pa.c (hppa_register_move_cost): Increase to 18 cost of
+       move from floating point to shift amount register .
+       (emit_move_sequence): Remove secondary reload support for floating
+       point to shift amount amount register copies.
+       (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
+       amount register copies.
+       * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
+       register, return false if mode isn't a scalar integer mode.
+       * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.
+
 2011-04-08  Richard Guenther  <rguenther@suse.de>
 
        * gimple.c (gimple_call_flags): Remove kludge.

diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index ab6485199b6a14904777e6b5723ba54ae909acb1..21b62de3569700707935e3b7e282ee7cdd2535bf 100644 (file)
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1447,6 +1447,8 @@ hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
 {
   if (from == SHIFT_REGS)
     return 0x100;
+  else if (to == SHIFT_REGS && FP_REG_CLASS_P (from))
+    return 18;
   else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to))
            || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from)))
     return 16;
@@ -1790,15 +1792,12 @@ emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
       return 1;
     }
   /* Handle secondary reloads for SAR.  These occur when trying to load
-     the SAR from memory, FP register, or with a constant.  */
+     the SAR from memory or a constant.  */
   else if (scratch_reg
           && GET_CODE (operand0) == REG
           && REGNO (operand0) < FIRST_PSEUDO_REGISTER
           && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
-          && (GET_CODE (operand1) == MEM
-              || GET_CODE (operand1) == CONST_INT
-              || (GET_CODE (operand1) == REG
-                  && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
+          && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
     {
       /* D might not fit in 14 bits either; for such cases load D into
         scratch reg.  */
@@ -5863,6 +5862,10 @@ output_arg_descriptor (rtx call_insn)
   fputc ('\n', asm_out_file);
 }
 \f
+/* Inform reload about cases where moving X with a mode MODE to a register in
+   RCLASS requires an extra scratch or immediate register.  Return the class
+   needed for the immediate register.  */
+
 static reg_class_t
 pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
                     enum machine_mode mode, secondary_reload_info *sri)
@@ -5965,24 +5968,29 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
       return NO_REGS;
     }
 
-  /* We need a secondary register (GPR) for copies between the SAR
-     and anything other than a general register.  */
-  if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32))
+  /* A SAR<->FP register copy requires an intermediate general register
+     and secondary memory.  We need a secondary reload with a general
+     scratch register for spills.  */
+  if (rclass == SHIFT_REGS)
     {
-      sri->icode = (in_p
-                   ? direct_optab_handler (reload_in_optab, mode)
-                   : direct_optab_handler (reload_out_optab, mode));
-      return NO_REGS;
+      /* Handle spill.  */
+      if (regno >= FIRST_PSEUDO_REGISTER || regno < 0)
+       {
+         sri->icode = (in_p
+                       ? direct_optab_handler (reload_in_optab, mode)
+                       : direct_optab_handler (reload_out_optab, mode));
+         return NO_REGS;
+       }
+
+      /* Handle FP copy.  */
+      if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))
+       return GENERAL_REGS;
     }
 
-  /* A SAR<->FP register copy requires a secondary register (GPR) as
-     well as secondary memory.  */
   if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
-      && (REGNO_REG_CLASS (regno) == SHIFT_REGS
-      && FP_REG_CLASS_P (rclass)))
-    sri->icode = (in_p
-                 ? direct_optab_handler (reload_in_optab, mode)
-                 : direct_optab_handler (reload_out_optab, mode));
+      && REGNO_REG_CLASS (regno) == SHIFT_REGS
+      && FP_REG_CLASS_P (rclass))
+    return GENERAL_REGS;
 
   return NO_REGS;
 }

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index d207c0a72757e78c0cbf19c3c68610a0f73742fe..a209773160a6a9dacdb1f6c4f82fdffa77269451 100644 (file)
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -209,6 +209,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    registers.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
   ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode               \
+   : (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE)                          \
    : !TARGET_PA_11 && FP_REGNO_P (REGNO)                               \
      ? (VALID_FP_MODE_P (MODE)                                         \
        && (GET_MODE_SIZE (MODE) <= 8                                   \

diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h
index 810e945f6b41cb39e13aa350fdd0cd91a4889a91..b5f04309fbc1cc960e274f80ae9a7ab74198a0c8 100644 (file)
--- a/gcc/config/pa/pa64-regs.h
+++ b/gcc/config/pa/pa64-regs.h
@@ -149,10 +149,11 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
    On the HP-PA, the cpu registers can hold any mode.  We
-   force this to be an even register is it cannot hold the full mode.  */
+   force this to be an even register if it cannot hold the full mode.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
   ((REGNO) == 0                                                                \
    ? (MODE) == CCmode || (MODE) == CCFPmode                            \
+   : (REGNO) == 60 ? SCALAR_INT_MODE_P (MODE)                          \
    /* Make wide modes be in aligned registers.  */                     \
    : FP_REGNO_P (REGNO)                                                        \
      ? (VALID_FP_MODE_P (MODE)                                         \