This was assuming that unused temporaries are written but never read,
since the NOP register can only be used as a destination register,
but we can end up here also for temporaries that are read once but
never written.
This was found with a graphicsfuzz test that has a switch with
cases that have unreachable discards. In that test, NIR genrates
code like this:
decl_reg vec3 32 r19
...
r20 = mov r19.z
r21 = mov r19.y
r22 = mov r19.x
Where r19.xyz would generate 3 temporary registers that are read but
never written, so we would rewrite them to point to the NOP register
as QPU instruction sources, which is not allowed and would hit an
assert that expect magic reads to be from [r0,r5] only.
Fixes:
dEQP-VK.graphicsfuzz.unreachable-switch-case-with-discards
Reviewed-by: Alejandro PiƱeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5645>
temp_registers[i].magic = false;
temp_registers[i].index = ra_reg - PHYS_INDEX;
}
-
- /* If the value's never used, just write to the NOP register
- * for clarity in debug output.
- */
- if (c->temp_start[i] == c->temp_end[i]) {
- temp_registers[i].magic = true;
- temp_registers[i].index = V3D_QPU_WADDR_NOP;
- }
}
ralloc_free(g);