struct {
GLuint resource_min_lod:12;
- GLuint pad0:16;
+
+ /* Only on Haswell */
+ GLuint pad0:4;
+ GLuint shader_chanel_select_a:3;
+ GLuint shader_chanel_select_b:3;
+ GLuint shader_chanel_select_g:3;
+ GLuint shader_chanel_select_r:3;
+
GLuint alpha_clear_color:1;
GLuint blue_clear_color:1;
GLuint green_clear_color:1;
* - cache_control
*/
+ if (brw->intel.is_haswell) {
+ surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
+ surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ }
+
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
brw->wm.surf_offset[surf_index] +
surf->ss3.pitch = (16 - 1); /* ignored */
gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
+ if (brw->intel.is_haswell) {
+ surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
+ surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ }
+
/* Emit relocation to surface contents. Section 5.1.1 of the gen4
* bspec ("Data Cache") says that the data cache does not exist as
* a separate cache and is just the sampler cache.
gen7_set_surface_tiling(surf, region->tiling);
surf->ss3.pitch = (region->pitch * region->cpp) - 1;
+ if (intel->is_haswell) {
+ surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
+ surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ }
+
drm_intel_bo_emit_reloc(brw->intel.batch.bo,
brw->wm.surf_offset[unit] +
offsetof(struct gen7_surface_state, ss1),