Add option to set start pc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 40be110cf3190a5123e58a6fbc15d52e7394eb63..59c4f0ed19fab07e697c7981827b0daa38a2e11a 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -23,10 +23,11 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(const char* isa, size_t nprocs, bool halted,
+sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
              std::vector<std::pair<reg_t, mem_t*>> mems,
              const std::vector<std::string>& args)
   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
+    start_pc(start_pc),
     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
 {
   signal(SIGINT, &handle_signal);
@@ -227,14 +228,23 @@ static std::string dts_compile(const std::string& dts)
 
 void sim_t::make_dtb()
 {
-  uint32_t reset_vec[] = {
-    0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE
-    0x597,                              // auipc a1, 0
-    0x58593,                            // addi a1, a1, 0
-    0xf1402573,                                // csrr a0,mhartid
-    0x00028067                          // jalr zero, t0, 0 (jump straight to DRAM_BASE)
+  const int reset_vec_size = 8;
+
+  reg_t pc_delta = start_pc - DEFAULT_RSTVEC;
+  reg_t pc_delta_hi = (pc_delta + 0x800U) & ~reg_t(0xfffU);
+  reg_t pc_delta_lo = pc_delta - pc_delta_hi;
+  if ((pc_delta_hi >> 31) != 0 && (pc_delta_hi >> 31) != reg_t(-1) >> 31) {
+    fprintf(stderr, "initial pc %" PRIx64 " out of range\n", pc_delta);
+    abort();
+  }
+
+  uint32_t reset_vec[reset_vec_size] = {
+    0x297 + uint32_t(pc_delta_hi),              // auipc t0, &pc
+    0x597,                                      // auipc a1, &dtb
+    0x58593 + ((reset_vec_size - 1) * 4 << 20), // addi a1, a1, &dtb
+    0xf1402573,                                 // csrr a0, mhartid
+    0x28067 + uint32_t(pc_delta_lo << 20)       // jalr zero, t0, &pc
   };
-  reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
 
   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 

diff --git a/riscv/sim.h b/riscv/sim.h
index ea49e1852cbbcc08ed9fe00c5ad0d047f050b11c..b2181baed73e08802556be848d2631b1abd5cb70 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -19,7 +19,7 @@ class gdbserver_t;
 class sim_t : public htif_t
 {
 public:
-  sim_t(const char* isa, size_t _nprocs,  bool halted,
+  sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,
         std::vector<std::pair<reg_t, mem_t*>> mems,
         const std::vector<std::string>& args);
   ~sim_t();
@@ -38,6 +38,7 @@ private:
   std::vector<std::pair<reg_t, mem_t*>> mems;
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
+  reg_t start_pc;
   std::string dts;
   std::unique_ptr<rom_device_t> boot_rom;
   std::unique_ptr<clint_t> clint;

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 80c5fa6a12b51727f8f5e5ff3b5bd740ae2b044f..5abdf2412eeb0fe615b762281b123682a48ab917 100644 (file)
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -27,6 +27,7 @@ static void help()
   fprintf(stderr, "  -h                    Print this help message\n");
   fprintf(stderr, "  -H                 Start halted, allowing a debugger to connect\n");
   fprintf(stderr, "  --isa=<name>          RISC-V ISA string [default %s]\n", DEFAULT_ISA);
+  fprintf(stderr, "  --pc=<address>        Set the initial program counter [default 0x80000000]\n");
   fprintf(stderr, "  --ic=<S>:<W>:<B>      Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>        W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>        B both powers of 2).\n");
@@ -64,22 +65,6 @@ static std::vector<std::pair<reg_t, mem_t*>> make_mems(const char* arg)
     arg = p + 1;
   }
   return res;
-#if 0
-  // allocate target machine's memory, shrinking it as necessary
-  // until the allocation succeeds
-  size_t memsz0 = (size_t)mem_mb << 20;
-  size_t quantum = 1L << 20;
-  if (memsz0 == 0)
-    memsz0 = (size_t)2048 << 20;
-
-  memsz = memsz0;
-  while ((mem = (char*)calloc(1, memsz)) == NULL)
-    memsz = (size_t)(memsz*0.9)/quantum*quantum;
-
-  if (memsz != memsz0)
-    fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
-            memsz, memsz0);
-#endif
 }
 
 int main(int argc, char** argv)
@@ -90,6 +75,7 @@ int main(int argc, char** argv)
   bool log = false;
   bool dump_dts = false;
   size_t nprocs = 1;
+  reg_t start_pc = DRAM_BASE;
   std::vector<std::pair<reg_t, mem_t*>> mems;
   std::unique_ptr<icache_sim_t> ic;
   std::unique_ptr<dcache_sim_t> dc;
@@ -109,6 +95,7 @@ int main(int argc, char** argv)
   // I wanted to use --halted, but for some reason that doesn't work.
   parser.option('H', 0, 0, [&](const char* s){halted = true;});
   parser.option(0, "gdb-port", 1, [&](const char* s){gdb_port = atoi(s);});
+  parser.option(0, "pc", 1, [&](const char* s){start_pc = strtoull(s, 0, 0);});
   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
@@ -128,7 +115,7 @@ int main(int argc, char** argv)
   if (mems.empty())
     mems = make_mems("2048");
 
-  sim_t s(isa, nprocs, halted, mems, htif_args);
+  sim_t s(isa, nprocs, halted, start_pc, mems, htif_args);
   std::unique_ptr<gdbserver_t> gdbserver;
   if (gdb_port) {
     gdbserver = std::unique_ptr<gdbserver_t>(new gdbserver_t(gdb_port, &s));