abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index c2d076c86341817c891dc629eb13d169430b26ce..66ddbde33442b99a148237760d26aaa417e11163 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -318,7 +318,7 @@ struct XAigerWriter
 
                        RTLIL::Module* box_module = module->design->module(cell->type);
                        log_assert(box_module);
-                       log_assert(box_module->attributes.count("\\abc9_box_id"));
+                       log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
 
                        auto r = box_ports.insert(cell->type);
                        if (r.second) {

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 4d05b5afbb97004472fbd393c7dfcf32d77d95a2..fd2759ae5c3615ade56e56448b97f7ab14484eba 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -117,7 +117,7 @@ void check(RTLIL::Design *design)
                                if (wire->port_output) num_outputs++;
                        }
                        if (num_outputs != 1)
-                               log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+                               log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
                }
        }
 }
@@ -333,7 +333,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
                log_assert(cell);
 
                RTLIL::Module* box_module = design->module(cell->type);
-               if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
+               if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
                        continue;
 
                cell->attributes["\\abc9_box_seq"] = box_count++;