--- /dev/null
+Introduction
+############
+
+MigScope is a small logic analyzer to be embedded in an FPGA.
+
+While free vendor's toolchains are generally used by beginners or for prototyping (situations where having a logic analyser in the design is generally very helpfull) free toolchains are always provided without the proprietary logic analyzer solution...:(
+
+Based on Migen, MigScope aims to provide a free and more portable / flexible alternative to vendor's solutions.
+
+About Migen
+***********
+Migen is a Python-based tool that aims at automating further the VLSI design process. [*]_
+
+.. [*] More information on Migen on : http://github.com/milkymist/migen
+
+Migen makes it possible to apply modern software concepts such as object-oriented programming and metaprogramming to design hardware. This results in more elegant and easily maintained designs and reduces the incidence of human errors.
+
+Installing MigScope
+*******************
+Either run the setup.py installation script or simply set PYTHONPATH to the
+root of the source directory.
+
+Feedback
+********
+Feedback concerning MigScope or this manual should be sent to florent@enjoy-digital.fr
+
+
+The MigScope Structure
+######################
+
+Migscope provides two kinds of cores:
+
+ - MigIo : the virtual Input / Output core
+ - MigLa : the virtual Logic Analyser core
+
+A CSR bus controls the MigIo and MigLa cores.The CSR bus is a very simple bus originally used to control peripheral's registers in milkymist Soc.[*]_
+
+.. [*] More information on Milkymist on : http://github.com/milkymist/milkymist-ng
+
+Because it's simplicity, it can be adapted very easily to a wide range of interfaces: Wishbone, Uart, Spi, I2C, Ethernet...
+
+MigScope uses CSR library from Migen to inter-connect cores. MigScope provides a Spi2Csr Bridge and is tested with an external Spi Interface. Support of others external interface will be added in future versions.
+
+Because Migen is a Python-based tool, using Python to control MigScope gives us lot's of advantages : Python Class can provides the HDL description **AND** the driver functions!
+
+*MigScope Structure Schematic*
+
+MigIo
+#####
+
+Description
+-----------
+
+The MigIo is simply an internal GPIO equivalent. It provides N (configurable) inputs and/or outputs and can be used for lot's of purposes:
+
+ - stimulation of a core's parameters in a design where external control interface is not yet developped or still under developpement.
+ - update of a Look-Up-Table or a Ram in the design.
+ - read an internal / external bus values
+ - ...
+
+*MigIo Structure Schematic*
+
+
+Instanciation
+-------------
+::
+
+ MIGIO_ADDR = 0x0000
+ migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
+
+MigIo parameters are:
+
+ - CSR address : core base Address
+ - Bus width : size of input / output buses. **(a power of two)**
+ - mode : "I" for input, "O" for output, "IO" for both
+
+Driver
+------
+To use drivers functions, an interface must be defined::
+
+ csr = Uart2Spi(1,115200)
+ migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr)
+
+MigIo drivers functions will now use our csr interface. Note that it is only useful to define the migIo interface in the Python code that will be executed on the Host, the code that will be translated in HDL don't need it.
+
+Write Method::
+
+ migIo0.write(0x1234, 0x5A)
+Write parameters are:
+
+ - CSR Address
+ - Data
+
+Read Method::
+
+ migIo0.read(0x1234)
+
+Read parameters are:
+
+ - CSR Address
+
+Example Design
+--------------
+
+de0_nano and de1 examples instanciate a MigIo Core.
+
+The HDL Code is in examples/deX/top.py
+
+The Host Code is in examples/deX/client/test_MigIo.py
+
+MigLa
+#####
\ No newline at end of file
--- /dev/null
+#!/usr/bin/env python3
+
+import sys, os
+from setuptools import setup
+from setuptools import find_packages
+
+here = os.path.abspath(os.path.dirname(__file__))
+README = open(os.path.join(here, "README")).read()
+
+required_version = (3, 1)
+if sys.version_info < required_version:
+ raise SystemExit("MigScope requires python {0} or greater".format(
+ ".".join(map(str, required_version))))
+
+setup(
+ name="migscope",
+ version="unknown",
+ description="Migen based Fpga logic analyzer",
+ long_description=README,
+ author="Florent Kermarrec",
+ author_email="florent@enjoy-digital.fr",
+ url="http://enjoy-digital.fr",
+ download_url="https://github.com/Florent-Kermarrec/migScope",
+ packages=find_packages(here),
+ license="GPL",
+ platforms=["Any"],
+ keywords="HDL ASIC FPGA hardware design",
+ classifiers=[
+ "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+ "Environment :: Console",
+ "Development Status :: Alpha",
+ "Intended Audience :: Developers",
+ "License :: OSI Approved :: GNU General Public License (GPL)",
+ "Operating System :: OS Independent",
+ "Programming Language :: Python",
+ ],
+)
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