soc/add_cpu: simplify CPUNone integration

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index afcf6a172391d3fe56d689a8f437361385d454f8..b932d4decd5f6180a89804ab67d641056db71e11 100644 (file)
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -18,6 +18,8 @@ class CPU(Module):
     interrupts           = {}
     mem_map              = {}
     io_regions           = {}
+    def __init__(self, *args, **kwargs):
+        pass
 
 class CPUNone(CPU):
     data_width           = 32
@@ -35,6 +37,7 @@ from litex.soc.cores.cpu.rocket import RocketRV64
 from litex.soc.cores.cpu.microwatt import Microwatt
 
 CPUS = {
+    "None"       : CPUNone,
     "lm32"       : LM32,
     "mor1kx"     : MOR1KX,
     "picorv32"   : PicoRV32,

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index c5ecf11d9d9cff79e8125dcbeda208a5e31495eb..22a87ff6854ab2796df8043698757b6e7535ee27 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -737,24 +737,26 @@ class SoC(Module):
                 colorer(name, color="red"),
                 colorer(", ".join(cpu.CPUS.keys()), color="green")))
             raise
-        # Add CPU + Bus Masters + CSR + IRQs
+        # Add CPU
         self.submodules.cpu = cpu.CPUS[name](self.platform, variant)
-        self.cpu.set_reset_address(reset_address)
-        for n, cpu_bus in enumerate(self.cpu.buses):
-            self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
-        self.add_csr("cpu", use_loc_if_exists=True)
-        for name, loc in self.cpu.interrupts.items():
-            self.irq.add(name, loc)
-        if hasattr(self, "ctrl"):
-            self.comb += self.cpu.reset.eq(self.ctrl.reset)
+        # Add Bus Masters/CSR/IRQs
+        if not isinstance(self.cpu, cpu.CPUNone):
+            self.cpu.set_reset_address(reset_address)
+            for n, cpu_bus in enumerate(self.cpu.buses):
+                self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
+            self.add_csr("cpu", use_loc_if_exists=True)
+            for name, loc in self.cpu.interrupts.items():
+                self.irq.add(name, loc)
+            if hasattr(self, "ctrl"):
+                self.comb += self.cpu.reset.eq(self.ctrl.reset)
+            self.add_config("CPU_RESET_ADDR", reset_address)
         # Update SoC with CPU constraints
         for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
             self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
         self.mem_map.update(self.cpu.mem_map) # FIXME
-        # Define constants
-        self.add_config("CPU_TYPE",       str(name))
-        self.add_config("CPU_VARIANT",    str(variant.split('+')[0]))
-        self.add_config("CPU_RESET_ADDR", reset_address)
+        # Add constants
+        self.add_config("CPU_TYPE",    str(name))
+        self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
 
     def add_timer(self, name="timer0"):
         self.check_if_exists(name)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 55f73f75c4c591b3b512a1e15f720bd29e08f2a4..12560f081cb6115fdcff3b40515cea52613fdbc4 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -136,15 +136,10 @@ class SoCCore(LiteXSoC):
             self.add_controller("ctrl")
 
         # Add CPU
-        if cpu_type is not None:
-            self.add_cpu(
-                name          = cpu_type,
-                variant       = "standard" if cpu_variant is None else cpu_variant,
-                reset_address = self.mem_map["rom"] if integrated_rom_size else cpu_reset_address)
-        else:
-            self.submodules.cpu = cpu.CPUNone()
-            for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
-                self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
+        self.add_cpu(
+            name          = str(cpu_type),
+            variant       = "standard" if cpu_variant is None else cpu_variant,
+            reset_address = self.mem_map["rom"] if integrated_rom_size else cpu_reset_address)
 
         # Add User's interrupts
         for name, loc in self.interrupt_map.items():
@@ -286,7 +281,7 @@ def soc_core_argdict(args):
 class SoCMini(SoCCore):
      def __init__(self, *args, **kwargs):
         if "cpu_type" not in kwargs.keys():
-            kwargs["cpu_type"] = None
+            kwargs["cpu_type"] = "None"
         if "integrated_sram_size" not in kwargs.keys():
             kwargs["integrated_sram_size"] = 0
         if "with_uart" not in kwargs.keys():