dev-arm: ambiguous use of getPort()

The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.

This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)

Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index f043db29eb1fd8fd646add878bf1a0189cf3c92f..6235c223c3b7ca9e59b01495a16bf93bc072bed9 100644 (file)
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -132,9 +132,9 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault,
     }
 
     if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
-        parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
-                                   event, data, tc->getCpuPtr()->clockPeriod(),
-                                   req->getFlags());
+        parent.getDMAPort().dmaAction(
+            MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
+            tc->getCpuPtr()->clockPeriod(), req->getFlags());
     } else {
         // We can't do the DMA access as there's been a problem, so tell the
         // event we're done

diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 8787089dc9cba7fa009e0e81243c86ec448c2f89..69f2f52b8419cebd2e0d6bc988b6218649b25c3e 100644 (file)
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -110,7 +110,7 @@ class Stage2MMU : public SimObject
      * is used by the two table walkers, and is exposed externally and
      * connected through the stage-one table walker.
      */
-    DmaPort& getPort() { return port; }
+    DmaPort& getDMAPort() { return port; }
 
     Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
         uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 21257de59ede1a390c6251036a90dad9e1419926..d310e9ee69637519e2e10cfde7fd59d9a525141b 100644 (file)
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -102,7 +102,7 @@ void
 TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
 {
     stage2Mmu = m;
-    port = &m->getPort();
+    port = &m->getDMAPort();
     masterId = master_id;
 }
 

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index dc3c35bab9ee85ee93b8657ba10b28c93032aa02..47c5f966f5a48b0fa01cb3d0a28b9e15b52007ab 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1246,7 +1246,7 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
 Port *
 TLB::getTableWalkerPort()
 {
-    return &stage2Mmu->getPort();
+    return &stage2Mmu->getDMAPort();
 }
 
 void