Merge remote-tracking branch 'origin/master' into xaig

diff --cc Makefile
Simple merge

diff --cc frontends/aiger/aigerparse.cc
index db5f9d2b91a0ef6df2c70ee710efac26cb282a12,2e4774dfdc32433feb3f2a63f3499953c2a91c02..4e3f5e7c944bc202b5abfcf81d0262cd950467e7
--- 1/frontends/aiger/aigerparse.cc
--- 2/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -35,11 -33,8 +35,8 @@@
  
  YOSYS_NAMESPACE_BEGIN
  
- //#define log_debug log
- #define log_debug(...) ;
- 
 -AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
 -    : design(design), f(f), clk_name(clk_name)
 +AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
 +    : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
  {
      module = new RTLIL::Module;
      module->name = module_name;

diff --cc kernel/rtlil.h
Simple merge

diff --cc techlibs/ice40/cells_sim.v
Simple merge

diff --cc techlibs/xilinx/synth_xilinx.cc
index 8a531c49727418ed8761591e7a94088fd009b482,d66722195e0af30a3bd69ebe4d01663c29c68dbc..08d74cd3b364f93011e734fb3c29c4bb761b64d6
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -277,14 -276,9 +284,9 @@@ struct SynthXilinxPass : public Pas
                if (check_label(active, run_from, run_to, "map_luts"))
                {
                        Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
 -                      Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 +                      Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
                        Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
-               }
- 
-               if (check_label(active, run_from, run_to, "map_cells"))
-               {
-                       Pass::call(design, "techmap -map +/xilinx/cells_map.v");
                        Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
                                        "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
                        Pass::call(design, "clean");