Add log2ceil and use it in bram code

We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
memory bits.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/utils.vhdl b/utils.vhdl
index 7238641f528e6407342abca58349baf446aa8ac4..4ccc3b56592aed8234c8a8ac262b88c0fdd53318 100644 (file)
--- a/utils.vhdl
+++ b/utils.vhdl
@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 package utils is
 
     function log2(i : natural) return integer;
+    function log2ceil(i : natural) return integer;
     function ispow2(i : integer) return boolean;
 
 end utils;
@@ -22,6 +23,17 @@ package body utils is
         return ret;
     end function;
 
+    function log2ceil(i : natural) return integer is
+        variable tmp : integer := i;
+        variable ret : integer := 0;
+    begin
+        while tmp >= 1 loop
+            ret  := ret + 1;
+            tmp := tmp / 2;
+        end loop;
+        return ret;
+    end function;
+
     function ispow2(i : integer) return boolean is
     begin
         if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index 14520b5458ab776d5af2313ceec9433ce627b2bc..2cf2a17a28e14140218eee9928c33df4d8314cf0 100644 (file)
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;
 
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
 
     -- RAM interface
     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);