sim: bfin: note missing parallel handling of SEARCH

The SEARCH insn is an oddball when it comes to parallel usage.  It places a
big limit on what other insns it can run in parallel with, but we don't
currently track the amount of state needed to verify this (since no other insn
really requires this).  Add a note for now in case we get around to it.

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 17a75f138cef685681d7954aa903b94037f43385..343a891ad7e1a957539dccbbbf52292fe74f3c1c 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,8 @@
+2013-06-23  Mike Frysinger  <vapier@gentoo.org>
+
+       * bfin-sim.c (decode_dsp32alu_0): Add note about broken handling of
+       SEARCH with parallel insns.
+
 2013-06-23  Mike Frysinger  <vapier@gentoo.org>
 
        * bfin-sim.c (decode_dsp32shift_0): Make sure HLs is 0 after last

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 90e09106c5b32c21dbc9a799e96bf18419febad6..484c4800b24eb61d411e40b1728fde11d13e8cf5 100644 (file)
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -5148,6 +5148,19 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       TRACE_INSN (cpu, "(R%i, R%i) = SEARCH R%i (%s);",
                  dst1, dst0, src0, searchmodes[aop]);
 
+      /* XXX: The parallel version is a bit weird in its limits:
+
+         This instruction can be issued in parallel with the combination of one
+         16-bit length load instruction to the P0 register and one 16-bit NOP.
+         No other instructions can be issued in parallel with the Vector Search
+         instruction. Note the following legal and illegal forms.
+         (r1, r0) = search r2 (LT) || r2 = [p0++p3]; // ILLEGAL
+         (r1, r0) = search r2 (LT) || r2 = [p0++];   // LEGAL
+         (r1, r0) = search r2 (LT) || r2 = [p0++];   // LEGAL
+
+         Unfortunately, our parallel insn state doesn't (currently) track enough
+         details to be able to check this.  */
+
       if (dst0 == dst1)
        illegal_instruction_combination (cpu);