Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort

diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py
index bedc603a03b031251d64648166d51ad70f7866dd..4bb4dd9f1026bd9effff929475ec2e2b451244cd 100644 (file)
--- a/milkymist/framebuffer/__init__.py
+++ b/milkymist/framebuffer/__init__.py
@@ -134,12 +134,12 @@ class FIFO(Module, Actor):
                        Instance.Output("data_out", fifo_data_out),
                        Instance.Output("empty"),
                        Instance.Input("read_en", 1),
-                       Instance.ClockPort("clk_read", "vga"),
+                       Instance.Input("clk_read", ClockSignal("vga")),
 
                        Instance.Input("data_in", fifo_data_in),
                        Instance.Output("full", fifo_full),
                        Instance.Input("write_en", fifo_write_en),
-                       Instance.ClockPort("clk_write"),
+                       Instance.Input("clk_write", ClockSignal()),
                        
                        Instance.Input("rst", 0))
                t = self.token("dac")

diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py
index 6f398498c811d70b786e273ba6194019c8935ca8..8792b01088d048768acde6ddc59dfb581d87dd76 100644 (file)
--- a/milkymist/lm32/__init__.py
+++ b/milkymist/lm32/__init__.py
@@ -15,8 +15,8 @@ class LM32(Module):
                i_adr_o = Signal(32)
                d_adr_o = Signal(32)
                self.specials += Instance("lm32_top",
-                       Instance.ClockPort("clk_i"),
-                       Instance.ResetPort("rst_i"),
+                       Instance.Input("clk_i", ClockSignal()),
+                       Instance.Input("rst_i", ResetSignal()),
                        
                        Instance.Input("interrupt", self.interrupt),
                        #Instance.Input("ext_break", self.ext_break),

diff --git a/milkymist/minimac3/__init__.py b/milkymist/minimac3/__init__.py
index 893ae374ca7c9ca0fa0912f07d72118f4e2fdc56..ce58bd7db8cd9a0fa91cbb2b4800c8228255b068 100644 (file)
--- a/milkymist/minimac3/__init__.py
+++ b/milkymist/minimac3/__init__.py
@@ -61,8 +61,8 @@ class MiniMAC(Module, AutoReg):
                        rx_pending_1_r.eq(rx_pending_1)
                ]
                self.specials += Instance("minimac3",
-                               Instance.ClockPort("sys_clk"),
-                               Instance.ResetPort("sys_rst"),
+                               Instance.Input("sys_clk", ClockSignal()),
+                               Instance.Input("sys_rst", ResetSignal()),
 
                                Instance.Output("rx_done_0", self.ev.rx0.trigger),
                                Instance.Output("rx_count_0", self._rx_count_0.field.w),
@@ -84,11 +84,11 @@ class MiniMAC(Module, AutoReg):
                                Instance.Output("wb_dat_o", self.membus.dat_r),
                                Instance.Output("wb_ack_o", self.membus.ack),
                                
-                               Instance.ClockPort("phy_tx_clk", "eth_tx"),
+                               Instance.Input("phy_tx_clk", ClockSignal("eth_tx")),
                                Instance.Output("phy_tx_data", self.phy_tx_data),
                                Instance.Output("phy_tx_en", self.phy_tx_en),
                                Instance.Output("phy_tx_er", self.phy_tx_er),
-                               Instance.ClockPort("phy_rx_clk", "eth_rx"),
+                               Instance.Input("phy_rx_clk", ClockSignal("eth_rx")),
                                Instance.Input("phy_rx_data", self.phy_rx_data),
                                Instance.Input("phy_dv", self.phy_dv),
                                Instance.Input("phy_rx_er", self.phy_rx_er),

diff --git a/milkymist/s6ddrphy/__init__.py b/milkymist/s6ddrphy/__init__.py
index 873f7d332a81b0d44c2317f3fe07c1a947503bf3..aad9db33e3e16c890eb16f1ea3ea3c9f7689387a 100644 (file)
--- a/milkymist/s6ddrphy/__init__.py
+++ b/milkymist/s6ddrphy/__init__.py
@@ -9,10 +9,10 @@ class S6DDRPHY(Module):
                        Instance.Parameter("NUM_AD", a),
                        Instance.Parameter("NUM_BA", ba),
                        Instance.Parameter("NUM_D", d),
-                       Instance.ClockPort("sys_clk"),
-                       Instance.ClockPort("clk2x_270", "sys2x_270"),
-                       Instance.ClockPort("clk4x_wr", "sys4x_wr"),
-                       Instance.ClockPort("clk4x_rd", "sys4x_rd")
+                       Instance.Input("sys_clk", ClockSignal()),
+                       Instance.Input("clk2x_270", ClockSignal("sys2x_270")),
+                       Instance.Input("clk4x_wr", ClockSignal("sys4x_wr")),
+                       Instance.Input("clk4x_rd", ClockSignal("sys4x_rd"))
                ]
                for name, width, cl in [
                        ("clk4x_wr_strb", 1, Instance.Input),