ruby: fixed cache index setting

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 91a76497ef18eacf7030a86de545f2819b3dd50f..2f7faab524a77f6187789fe210047e4dfdd7e50d 100644 (file)
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -68,15 +68,19 @@ def create_system(options, system, piobus, dma_devices):
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
     #
+    l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
         #
         l1i_cache = L1Cache(size = options.l1i_size,
-                            assoc = options.l1i_assoc)
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
         l1d_cache = L1Cache(size = options.l1d_size,
-                            assoc = options.l1d_assoc)
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
@@ -91,9 +95,7 @@ def create_system(options, system, piobus, dma_devices):
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
-                                      l2_select_num_bits = \
-                                        math.log(options.num_l2caches,
-                                                 2))
+                                      l2_select_num_bits = l2_bits)
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         
@@ -103,12 +105,15 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    l2_index_start = block_size_bits + l2_bits
+
     for i in xrange(options.num_l2caches):
         #
         # First create the Ruby objects associated with this cpu
         #
         l2_cache = L2Cache(size = options.l2_size,
-                           assoc = options.l2_assoc)
+                           assoc = options.l2_assoc,
+                           start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
                                       L2cacheMemory = l2_cache)

diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 0e101d18fb8351d5380e7677aeecdba4869cae40..82817d60a2cee623d36f6eafa71ec3555c6e0cb4 100644 (file)
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -60,6 +60,7 @@ def create_system(options, system, piobus, dma_devices):
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
     #
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     
     for i in xrange(options.num_cpus):
         #
@@ -68,7 +69,8 @@ def create_system(options, system, piobus, dma_devices):
         # config parameters.
         #
         cache = Cache(size = options.l1d_size,
-                      assoc = options.l1d_assoc)
+                      assoc = options.l1d_assoc,
+                      start_index_bit = block_size_bits)
 
         #
         # Only one unified L1 cache exists.  Can cache instructions and data.

diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 11b65c39700a935d601d25177bff15c63d89612f..ff7ea0cc5b68bc2ea54600e6491d4a55a93f8599 100644 (file)
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -68,15 +68,19 @@ def create_system(options, system, piobus, dma_devices):
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
     #
+    l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
         #
         l1i_cache = L1Cache(size = options.l1i_size,
-                            assoc = options.l1i_assoc)
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
         l1d_cache = L1Cache(size = options.l1d_size,
-                            assoc = options.l1d_assoc)
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
@@ -91,9 +95,7 @@ def create_system(options, system, piobus, dma_devices):
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
-                                      l2_select_num_bits = \
-                                      math.log(options.num_l2caches,
-                                               2))
+                                      l2_select_num_bits = l2_bits)
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -102,12 +104,15 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    l2_index_start = block_size_bits + l2_bits
+
     for i in xrange(options.num_l2caches):
         #
         # First create the Ruby objects associated with this cpu
         #
         l2_cache = L2Cache(size = options.l2_size,
-                           assoc = options.l2_assoc)
+                           assoc = options.l2_assoc,
+                           start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
                                       L2cacheMemory = l2_cache)

diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 1e1190caeed92f90078e5e3ecfec4fced0d6ddf7..72721058bad5ae1c8952bf6197036fc3c83e3b5f 100644 (file)
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -82,15 +82,18 @@ def create_system(options, system, piobus, dma_devices):
     # controller constructors are called before the network constructor
     #
     l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
         #
         l1i_cache = L1Cache(size = options.l1i_size,
-                            assoc = options.l1i_assoc)
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
         l1d_cache = L1Cache(size = options.l1d_size,
-                            assoc = options.l1d_assoc)
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
@@ -123,13 +126,15 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+    l2_index_start = block_size_bits + l2_bits
+
     for i in xrange(options.num_l2caches):
         #
         # First create the Ruby objects associated with this cpu
         #
         l2_cache = L2Cache(size = options.l2_size,
                            assoc = options.l2_assoc,
-                           start_index_bit = l2_bits)
+                           start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
                                       L2cacheMemory = l2_cache,
@@ -158,9 +163,7 @@ def create_system(options, system, piobus, dma_devices):
                                                              size = \
                                                                dir_size),
                                          memBuffer = mem_cntrl,
-                                         l2_select_num_bits = \
-                                           math.log(options.num_l2caches,
-                                                    2))
+                                         l2_select_num_bits = l2_bits)
 
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index d0552263ea143402bd6454d5b52ac8812dec1fbb..3804a58b1651c54db81b84463342dd4b392234dd 100644 (file)
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -78,17 +78,21 @@ def create_system(options, system, piobus, dma_devices):
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
     #
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
         #
         l1i_cache = L1Cache(size = options.l1i_size,
-                            assoc = options.l1i_assoc)
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
         l1d_cache = L1Cache(size = options.l1d_size,
-                            assoc = options.l1d_assoc)
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
         l2_cache = L2Cache(size = options.l2_size,
-                           assoc = options.l2_assoc)
+                           assoc = options.l2_assoc,
+                           start_index_bit = block_size_bits)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,