radeonsi: Enable DCC.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 1eec596b2587809d73bb3b278da4974a0405e290..f21a0b3a1888b94d6591714f03bdbf5de8846fd9 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -244,6 +244,7 @@ struct r600_surface {
        unsigned cb_color_dim;          /* EG only */
        unsigned cb_color_pitch;        /* EG and later */
        unsigned cb_color_slice;        /* EG and later */
+       unsigned cb_dcc_base;           /* VI and later */
        unsigned cb_color_attrib;       /* EG and later */
        unsigned cb_dcc_control;        /* VI and later */
        unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index c2a692c9af16771c4a72a985df4df79b17b89ece..031404976296923cc65976a498e1ea8dfccbd5bc 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -495,6 +495,8 @@ static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
 
        r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
                                 0xFFFFFFFF, true);
+
+       rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
 }
 
 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,

diff --git a/src/gallium/drivers/radeon/r600d_common.h b/src/gallium/drivers/radeon/r600d_common.h
index 115042d153ec35179f1f2c2e9c813ceeb4b92b86..a3d182cd30fda1d24b6e348b10f28fd6b2d54576 100644 (file)
--- a/src/gallium/drivers/radeon/r600d_common.h
+++ b/src/gallium/drivers/radeon/r600d_common.h
@@ -202,6 +202,7 @@
 
 #define   EG_S_028C70_FAST_CLEAR(x)                       (((x) & 0x1) << 17)
 #define   SI_S_028C70_FAST_CLEAR(x)                       (((x) & 0x1) << 13)
+#define   VI_S_028C70_DCC_ENABLE(x)                       (((x) & 0x1) << 28)
 
 /*CIK+*/
 #define R_0300FC_CP_STRMOUT_CNTL                    0x0300FC

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 13738da5e2c06af3060648a268f584c4af0d3cf1..5548cba3a24a25ff344bd96836f2522818203562 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -181,6 +181,11 @@ static void si_set_sampler_view(struct si_context *sctx, unsigned shader,
                                rview->resource, RADEON_USAGE_READ,
                                r600_get_sampler_view_priority(rview->resource));
 
+               if (rview->dcc_buffer && rview->dcc_buffer != rview->resource)
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
+                               rview->dcc_buffer, RADEON_USAGE_READ,
+                               RADEON_PRIO_DCC);
+
                pipe_sampler_view_reference(&views->views[slot], view);
                memcpy(views->desc.list + slot*8, view_desc, 8*4);
                views->desc.enabled_mask |= 1llu << slot;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 53529779481edd001011c689769b4d617a0870ba..42cd8803c365dfa54e9153aafb1d4124e4341284 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -98,6 +98,7 @@ struct si_sampler_view {
        struct pipe_sampler_view        base;
        struct list_head                list;
        struct r600_resource            *resource;
+       struct r600_resource            *dcc_buffer;
         /* [0..7] = image descriptor
          * [4..7] = buffer descriptor */
        uint32_t                        state[8];

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 264ab1b3817188da8aa2d6d329d94990090b62d0..384c8e28faafe080ee4bf7403bec5280b1b41a1c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1926,8 +1926,25 @@ static void si_initialize_color_surface(struct si_context *sctx,
        surf->cb_color_info = color_info;
        surf->cb_color_attrib = color_attrib;
 
-       if (sctx->b.chip_class >= VI)
-               surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
+       if (sctx->b.chip_class >= VI) {
+               unsigned max_uncompressed_block_size = 2;
+
+               if (rtex->surface.nsamples > 1) {
+                       if (rtex->surface.bpe == 1)
+                               max_uncompressed_block_size = 0;
+                       else if (rtex->surface.bpe == 2)
+                               max_uncompressed_block_size = 1;
+               }
+
+               surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
+                                      S_028C78_INDEPENDENT_64B_BLOCKS(1);
+
+               if (rtex->surface.dcc_enabled) {
+                       uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
+
+                       surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
+               }
+       }
 
        if (rtex->fmask.size) {
                surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
@@ -2251,6 +2268,12 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
                                RADEON_PRIO_CMASK);
                }
 
+               if (tex->dcc_buffer && tex->dcc_buffer != &tex->resource) {
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
+                               tex->dcc_buffer, RADEON_USAGE_READWRITE,
+                               RADEON_PRIO_DCC);
+               }
+
                radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
                                           sctx->b.chip_class >= VI ? 14 : 13);
                radeon_emit(cs, cb->cb_color_base);     /* R_028C60_CB_COLOR0_BASE */
@@ -2268,7 +2291,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
                radeon_emit(cs, tex->color_clear_value[1]);     /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
 
                if (sctx->b.chip_class >= VI)
-                       radeon_emit(cs, 0);     /* R_028C94_CB_COLOR0_DCC_BASE */
+                       radeon_emit(cs, cb->cb_dcc_base);       /* R_028C94_CB_COLOR0_DCC_BASE */
        }
        /* set CB_COLOR1_INFO for possible dual-src blending */
        if (i == 1 && state->cbufs[0] &&
@@ -2635,8 +2658,18 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
        view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
        view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
                          S_008F24_LAST_ARRAY(last_layer));
-       view->state[6] = 0;
-       view->state[7] = 0;
+
+       if (tmp->surface.dcc_enabled) {
+               uint64_t dcc_offset = surflevel[base_level].dcc_offset;
+               unsigned swap = r600_translate_colorswap(pipe_format);
+
+               view->state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
+               view->state[7] = (tmp->dcc_buffer->gpu_address + dcc_offset) >> 8;
+               view->dcc_buffer = tmp->dcc_buffer;
+       } else {
+               view->state[6] = 0;
+               view->state[7] = 0;
+       }
 
        /* Initialize the sampler view for FMASK. */
        if (tmp->fmask.size) {
@@ -3409,7 +3442,8 @@ static void si_init_config(struct si_context *sctx)
 
        if (sctx->b.chip_class >= VI) {
                si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
-                              S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
+                              S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
+                              S_028424_OVERWRITE_COMBINER_WATERMARK(4));
                si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
                si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
        }