Update existing testcase powerpc/bswap64-4.c to
reflect that we generate ldbrx and stdbrx instructions
for newer cpu targets, versus the pair of lwbrx and stwbrx
instructions as seen on previous cpu targets.
2020-03-24 Will Schmidt <will_schmidt@vnet.ibm.com>
gcc/testsuite/
* gcc.target/powerpc/bswap64-4.c: Update scan-assembler
expected results.
+2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * gcc.target/powerpc/bswap64-4.c: Update scan-assembler
+ expected results.
+
2020-03-30 Jakub Jelinek <jakub@redhat.com>
PR target/94343
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-O2 -mpowerpc64" } */
/* { dg-require-effective-target ilp32 } */
-/* { dg-final { scan-assembler-times "lwbrx" 2 } } */
-/* { dg-final { scan-assembler-times "stwbrx" 2 } } */
+/* { dg-final { scan-assembler-times "lwbrx" 2 { target { ! has_arch_pwr7 } } } } */
+/* { dg-final { scan-assembler-times "stwbrx" 2 { target { ! has_arch_pwr7 } } } } */
+/* { dg-final { scan-assembler-times "ldbrx" 1 { target has_arch_pwr7 } } } */
+/* { dg-final { scan-assembler-times "stdbrx" 1 { target has_arch_pwr7 } } } */
long long swap_load (long long *a) { return __builtin_bswap64 (*a); }
long long swap_reg (long long a) { return __builtin_bswap64 (a); }