*/
ctx = rmesa->glCtx;
- ctx->Const.MaxTextureUnits = 2;
- ctx->Const.MaxTextureImageUnits = 2;
- ctx->Const.MaxTextureCoordUnits = 2;
+ ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
+ "texture_units");
+ ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
+ ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
driCalculateMaxTextureLevels( rmesa->texture_heaps,
rmesa->nr_heaps,
_tnl_allow_vertex_fog( ctx, GL_TRUE );
- _math_matrix_ctr( &rmesa->TexGenMatrix[0] );
- _math_matrix_ctr( &rmesa->TexGenMatrix[1] );
+ for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
+ _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
+ _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
+ }
_math_matrix_ctr( &rmesa->tmpmat );
- _math_matrix_set_identity( &rmesa->TexGenMatrix[0] );
- _math_matrix_set_identity( &rmesa->TexGenMatrix[1] );
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
#define TEX_0 0x1
#define TEX_1 0x2
-#define TEX_ALL 0x3
+#define TEX_2 0x4
+#define TEX_3 0x8
+#define TEX_4 0x10
+#define TEX_5 0x20
+#define TEX_ALL 0x3f
typedef struct r200_tex_obj r200TexObj, *r200TexObjPtr;
GLenum envMode;
};
-#define R200_MAX_TEXTURE_UNITS 3
+#define R200_MAX_TEXTURE_UNITS 6
struct r200_texture_state {
struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS];
struct r200_state_atom cst;
struct r200_state_atom tam;
struct r200_state_atom tf;
- struct r200_state_atom tex[2];
- struct r200_state_atom cube[2];
+ struct r200_state_atom tex[6];
+ struct r200_state_atom cube[6];
struct r200_state_atom zbs;
struct r200_state_atom mtl[2];
- struct r200_state_atom mat[5];
+ struct r200_state_atom mat[9];
struct r200_state_atom lit[8]; /* includes vec, scl commands */
struct r200_state_atom ucp[6];
struct r200_state_atom pix[6]; /* pixshader stages */
GLuint prim;
};
-struct r200_vbinfo {
- GLint counter, initial_counter;
- GLint *dmaptr;
- void (*notify)( void );
- GLint vertex_size;
-
- /* A maximum total of 17 elements per vertex: 3 floats for position, 3
+ /* A maximum total of 29 elements per vertex: 3 floats for position, 3
* floats for normal, 4 floats for color, 4 bytes for secondary color,
- * 3 floats for each texture unit (6 floats total).
+ * 3 floats for each texture unit (18 floats total).
*
- * As soon as the 3rd through 6th TMUs are supported, this value will grow.
+ * we maybe need add. 4 to prevent segfault if someone specifies
+ * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: )
*
* The position data is never actually stored here, so 3 elements could be
* trimmed out of the buffer.
*/
- union { float f; int i; r200_color_t color; } vertex[17];
+
+#define R200_MAX_VERTEX_SIZE ((3*6)+11)
+
+struct r200_vbinfo {
+ GLint counter, initial_counter;
+ GLint *dmaptr;
+ void (*notify)( void );
+ GLint vertex_size;
+
+ union { float f; int i; r200_color_t color; } vertex[R200_MAX_VERTEX_SIZE];
GLfloat *normalptr;
GLfloat *floatcolorptr;
r200_color_t *colorptr;
GLfloat *floatspecptr;
r200_color_t *specptr;
- GLfloat *texcoordptr[2];
+ GLfloat *texcoordptr[8]; /* 6 (TMU) + 2 for r200_vtxfmt_c.c when GL_TEXTURE6/7 */
GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */
vfmt0 |= R200_VTX_FP_RGB << R200_VTX_COLOR_1_SHIFT;
component[nr++] = &rmesa->tcl.spec;
}
-
-/* vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & */
-/* ~(R200_TCL_VTX_Q0|R200_TCL_VTX_Q1|R200_TCL_VTX_Q2|R200_TCL_VTX_Q3|R200_TCL_VTX_Q4|R200_TCL_VTX_Q5)); */
re_cntl = rmesa->hw.set.cmd[SET_RE_CNTL] & ~(R200_VTX_STQ0_D3D |
R200_VTX_STQ1_D3D |
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
+ DRI_CONF_MAX_TEXTURE_UNITS(4,2,6)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 10;
+static const GLuint __driNConfigOptions = 11;
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
*/
-#define PCI_CHIP_R200_QD 0x5144
-#define PCI_CHIP_R200_QE 0x5145
+#define PCI_CHIP_R200_QD 0x5144 /* why do they have r200 names? */
+#define PCI_CHIP_R200_QE 0x5145 /* Those are all standard radeons */
#define PCI_CHIP_R200_QF 0x5146
#define PCI_CHIP_R200_QG 0x5147
#define PCI_CHIP_R200_QY 0x5159
#define PCI_CHIP_R200_LY 0x4C59
#define PCI_CHIP_R200_LZ 0x4C5A
#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
+#define PCI_CHIP_RV200_QX 0x5158
#define PCI_CHIP_RS100_4136 0x4136 /* IGP RS100, RS200, RS250 are not R200 */
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS300_5836 0x5836
#define PCI_CHIP_RS300_5837 0x5837
+#define PCI_CHIP_R200_BB 0x4242 /* r200 (non-derived) start */
+#define PCI_CHIP_R200_BC 0x4243
+#define PCI_CHIP_R200_QH 0x5148
+#define PCI_CHIP_R200_QI 0x5149
+#define PCI_CHIP_R200_QJ 0x514A
+#define PCI_CHIP_R200_QK 0x514B
+#define PCI_CHIP_R200_QL 0x514C
+#define PCI_CHIP_R200_QM 0x514D
+#define PCI_CHIP_R200_QN 0x514E
+#define PCI_CHIP_R200_QO 0x514F /* r200 (non-derived) end */
+/* are the R200 Qh (0x5168) and following needed too? They are not in xf86PciInfo.h
+ but in the pci database. Maybe just secondary ports or something ? */
+
#endif
#ifdef USE_NEW_INTERFACE
case PCI_CHIP_R200_QY:
case PCI_CHIP_R200_QZ:
case PCI_CHIP_RV200_QW:
+ case PCI_CHIP_RV200_QX:
case PCI_CHIP_R200_LW:
case PCI_CHIP_R200_LY:
case PCI_CHIP_R200_LZ:
case PCI_CHIP_RS300_5837:
break;
+ case PCI_CHIP_R200_BB:
+ case PCI_CHIP_R200_BC:
+ case PCI_CHIP_R200_QH:
+ case PCI_CHIP_R200_QI:
+ case PCI_CHIP_R200_QJ:
+ case PCI_CHIP_R200_QK:
+ case PCI_CHIP_R200_QL:
+ case PCI_CHIP_R200_QM:
+ case PCI_CHIP_R200_QN:
+ case PCI_CHIP_R200_QO:
+ screen->chipset |= R200_CHIPSET_REAL_R200;
+ /* fallthrough */
default:
screen->chipset |= R200_CHIPSET_TCL;
break;
/* chipset features */
#define R200_CHIPSET_TCL (1 << 0)
+#define R200_CHIPSET_REAL_R200 (1 << 1)
#define R200_NR_TEX_HEAPS 2
CHECK( always, GL_TRUE )
CHECK( never, GL_FALSE )
CHECK( tex_any, ctx->Texture._EnabledUnits )
+CHECK( tex_pair, (ctx->Texture.Unit[idx]._ReallyEnabled | ctx->Texture.Unit[idx & ~1]._ReallyEnabled))
CHECK( tex, ctx->Texture.Unit[idx]._ReallyEnabled )
+CHECK( tex_cube, ctx->Texture.Unit[idx]._ReallyEnabled & TEXTURE_CUBE_BIT)
CHECK( fog, ctx->Fog.Enabled )
TCL_CHECK( tcl, GL_TRUE )
TCL_CHECK( tcl_tex, ctx->Texture.Unit[idx]._ReallyEnabled )
ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
- ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
ALLOC_STATE( tf, tex_any, TF_STATE_SIZE, "TF/tfactor", 0 );
- ALLOC_STATE( tex[0], tex_any, TEX_STATE_SIZE, "TEX/tex-0", 0 );
- ALLOC_STATE( tex[1], tex_any, TEX_STATE_SIZE, "TEX/tex-1", 1 );
-
+ if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) {
+ /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
+ ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE, "TEX/tex-0", 0 );
+ ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE, "TEX/tex-1", 1 );
+ ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
+ }
+ else {
+ ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE, "TEX/tex-0", 0 );
+ ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE, "TEX/tex-1", 1 );
+ ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
+ }
+ ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE, "TEX/tex-2", 2 );
+ ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE, "TEX/tex-3", 3 );
+ ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE, "TEX/tex-4", 4 );
+ ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE, "TEX/tex-5", 5 );
if (rmesa->r200Screen->drmSupportsCubeMaps) {
- ALLOC_STATE( cube[0], tex_any, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
- ALLOC_STATE( cube[1], tex_any, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
+ ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
+ ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
+ ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
+ ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
+ ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
+ ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
}
else {
ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
+ ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
+ ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
+ ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
+ ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
}
ALLOC_STATE( tcl, tcl, TCL_STATE_SIZE, "TCL/tcl", 0 );
ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
+ ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
+ ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
+ ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
+ ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
ALLOC_STATE( pix[0], always, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
ALLOC_STATE( pix[1], tex, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
+ ALLOC_STATE( pix[2], tex, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
+ ALLOC_STATE( pix[3], tex, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
+ ALLOC_STATE( pix[4], tex, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
+ ALLOC_STATE( pix[5], tex, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
/* Fill in the packet headers:
rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1);
rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
+ rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2);
+ rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
+ rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3);
+ rmesa->hw.tex[3].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
+ rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4);
+ rmesa->hw.tex[4].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
+ rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5);
+ rmesa->hw.tex[5].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0);
rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0);
rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1);
rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1);
+ rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2);
+ rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2);
+ rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3);
+ rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3);
+ rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4);
+ rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4);
+ rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5);
+ rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5);
rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0);
rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1);
+ rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2);
+ rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3);
+ rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4);
+ rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5);
rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
+ rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
+ cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
+ rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
+ cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
+ rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
+ cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
+ rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
+ cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
for (i = 0 ; i < 8; i++) {
rmesa->hw.lit[i].cmd[LIT_CMD_0] =
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
+ /* FIXME: what are these numbers? */
_tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
- 22 * sizeof(GLfloat) );
+ 36 * sizeof(GLfloat) );
rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
rmesa->swtcl.RenderIndex = ~0;
R200_STATECHANGE( rmesa, set );
rmesa->hw.set.cmd[SET_RE_CNTL] |= (R200_VTX_STQ0_D3D |
- R200_VTX_STQ1_D3D);
+ R200_VTX_STQ1_D3D |
+ R200_VTX_STQ2_D3D |
+ R200_VTX_STQ3_D3D |
+ R200_VTX_STQ4_D3D |
+ R200_VTX_STQ5_D3D);
}
-
static void transition_to_hwtnl( GLcontext *ctx )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
R200_STATECHANGE( rmesa, set );
rmesa->hw.set.cmd[SET_RE_CNTL] &= ~(R200_VTX_STQ0_D3D |
- R200_VTX_STQ1_D3D);
+ R200_VTX_STQ1_D3D |
+ R200_VTX_STQ2_D3D |
+ R200_VTX_STQ3_D3D |
+ R200_VTX_STQ4_D3D |
+ R200_VTX_STQ5_D3D);
if (R200_DEBUG & DEBUG_FALLBACKS)
"Texgen unit 0",
"Texgen unit 1",
"Texgen unit 2",
- "User disable"
+ "Texgen unit 3",
+ "Texgen unit 4",
+ "Texgen unit 5",
+ "User disable",
+ "Bitmap as points"
};
#define R200_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
#define R200_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
#define R200_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
-#define R200_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
-#define R200_TCL_FALLBACK_BITMAP 0x100 /* draw bitmap with points */
-
-#define R200_MAX_TCL_VERTSIZE (4*4) /* using maos now... */
+#define R200_TCL_FALLBACK_TEXGEN_3 0x80 /* texgen, unit 3 */
+#define R200_TCL_FALLBACK_TEXGEN_4 0x100 /* texgen, unit 4 */
+#define R200_TCL_FALLBACK_TEXGEN_5 0x200 /* texgen, unit 5 */
+#define R200_TCL_FALLBACK_TCL_DISABLE 0x400 /* user disable */
+#define R200_TCL_FALLBACK_BITMAP 0x800 /* draw bitmap with points */
#define TCL_FALLBACK( ctx, bit, mode ) r200TclFallback( ctx, bit, mode )
{
R200_TXC_ARG_A_R0_COLOR,
R200_TXC_ARG_A_R1_COLOR,
- R200_TXC_ARG_A_R2_COLOR
+ R200_TXC_ARG_A_R2_COLOR,
+ R200_TXC_ARG_A_R3_COLOR,
+ R200_TXC_ARG_A_R4_COLOR,
+ R200_TXC_ARG_A_R5_COLOR
},
{
R200_TXC_ARG_A_R0_COLOR | R200_TXC_COMP_ARG_A,
R200_TXC_ARG_A_R1_COLOR | R200_TXC_COMP_ARG_A,
- R200_TXC_ARG_A_R2_COLOR | R200_TXC_COMP_ARG_A
+ R200_TXC_ARG_A_R2_COLOR | R200_TXC_COMP_ARG_A,
+ R200_TXC_ARG_A_R3_COLOR | R200_TXC_COMP_ARG_A,
+ R200_TXC_ARG_A_R4_COLOR | R200_TXC_COMP_ARG_A,
+ R200_TXC_ARG_A_R5_COLOR | R200_TXC_COMP_ARG_A
},
{
R200_TXC_ARG_A_R0_ALPHA,
R200_TXC_ARG_A_R1_ALPHA,
- R200_TXC_ARG_A_R2_ALPHA
+ R200_TXC_ARG_A_R2_ALPHA,
+ R200_TXC_ARG_A_R3_ALPHA,
+ R200_TXC_ARG_A_R4_ALPHA,
+ R200_TXC_ARG_A_R5_ALPHA
},
{
R200_TXC_ARG_A_R0_ALPHA | R200_TXC_COMP_ARG_A,
R200_TXC_ARG_A_R1_ALPHA | R200_TXC_COMP_ARG_A,
- R200_TXC_ARG_A_R2_ALPHA | R200_TXC_COMP_ARG_A
+ R200_TXC_ARG_A_R2_ALPHA | R200_TXC_COMP_ARG_A,
+ R200_TXC_ARG_A_R3_ALPHA | R200_TXC_COMP_ARG_A,
+ R200_TXC_ARG_A_R4_ALPHA | R200_TXC_COMP_ARG_A,
+ R200_TXC_ARG_A_R5_ALPHA | R200_TXC_COMP_ARG_A
},
};
{
R200_TXA_ARG_A_R0_ALPHA,
R200_TXA_ARG_A_R1_ALPHA,
- R200_TXA_ARG_A_R2_ALPHA
+ R200_TXA_ARG_A_R2_ALPHA,
+ R200_TXA_ARG_A_R3_ALPHA,
+ R200_TXA_ARG_A_R4_ALPHA,
+ R200_TXA_ARG_A_R5_ALPHA
},
{
R200_TXA_ARG_A_R0_ALPHA | R200_TXA_COMP_ARG_A,
R200_TXA_ARG_A_R1_ALPHA | R200_TXA_COMP_ARG_A,
- R200_TXA_ARG_A_R2_ALPHA | R200_TXA_COMP_ARG_A
+ R200_TXA_ARG_A_R2_ALPHA | R200_TXA_COMP_ARG_A,
+ R200_TXA_ARG_A_R3_ALPHA | R200_TXA_COMP_ARG_A,
+ R200_TXA_ARG_A_R4_ALPHA | R200_TXA_COMP_ARG_A,
+ R200_TXA_ARG_A_R5_ALPHA | R200_TXA_COMP_ARG_A
},
};
* reduces the amount of special-casing we have to do, alpha-only
* textures being a notable exception.
*/
+ /* Don't cache these results.
+ */
+ rmesa->state.texture.unit[unit].format = 0;
+ rmesa->state.texture.unit[unit].envMode = 0;
+
if ( !texUnit->_ReallyEnabled ) {
- /* Don't cache these results.
- */
- rmesa->state.texture.unit[unit].format = 0;
- rmesa->state.texture.unit[unit].envMode = 0;
if ( unit == 0 ) {
color_combine = R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO
| R200_TXC_ARG_C_DIFFUSE_COLOR | R200_TXC_OP_MADD;
GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB;
GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA;
- /* Don't cache these results.
- */
- rmesa->state.texture.unit[unit].format = 0;
- rmesa->state.texture.unit[unit].envMode = 0;
-
/* Step 1:
* Extract the color and alpha combine function arguments.
r200ContextPtr rmesa = R200_CONTEXT(ctx);
GLboolean ok;
GLuint dbg;
+ int i;
ok = (r200UpdateTextureUnit( ctx, 0 ) &&
- r200UpdateTextureUnit( ctx, 1 ));
+ r200UpdateTextureUnit( ctx, 1 ) &&
+ r200UpdateTextureUnit( ctx, 2 ) &&
+ r200UpdateTextureUnit( ctx, 3 ) &&
+ r200UpdateTextureUnit( ctx, 4 ) &&
+ r200UpdateTextureUnit( ctx, 5 ));
FALLBACK( rmesa, R200_FALLBACK_TEXTURE, !ok );
if (rmesa->TclFallback)
r200ChooseVertexState( ctx );
- /*
- * T0 hang workaround -------------
- */
-#if 1
- if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_ENABLE_MASK) == R200_TEX_0_ENABLE &&
- (rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK) > R200_MIN_FILTER_LINEAR) {
-
- R200_STATECHANGE(rmesa, ctx);
- R200_STATECHANGE(rmesa, tex[1]);
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE;
- rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
- rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] |= 0x08000000;
- }
- else {
- if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) &&
- (rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] & 0x08000000)) {
- R200_STATECHANGE(rmesa, tex[1]);
- rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~0x08000000;
- }
- }
-#endif
-
-#if 1
- /*
- * Texture cache LRU hang workaround -------------
- */
- dbg = 0x0;
- if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_0_ENABLE) &&
- ((((rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
- 0x04) == 0)))
- {
- dbg |= 0x02;
- }
- if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) &&
- ((((rmesa->hw.tex[1].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
- 0x04) == 0)))
- {
- dbg |= 0x04;
- }
+ if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) {
- if (dbg != rmesa->hw.tam.cmd[TAM_DEBUG3]) {
- R200_STATECHANGE( rmesa, tam );
- rmesa->hw.tam.cmd[TAM_DEBUG3] = dbg;
- if (0) printf("TEXCACHE LRU HANG WORKAROUND %x\n", dbg);
- }
-#endif
-}
+ /*
+ * T0 hang workaround -------------
+ * not needed for r200 derivatives?
+ */
+ if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_ENABLE_MASK) == R200_TEX_0_ENABLE &&
+ (rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK) > R200_MIN_FILTER_LINEAR) {
+
+ R200_STATECHANGE(rmesa, ctx);
+ R200_STATECHANGE(rmesa, tex[1]);
+ rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE;
+ rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
+ rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] |= 0x08000000;
+ }
+ else {
+ if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) &&
+ (rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] & 0x08000000)) {
+ R200_STATECHANGE(rmesa, tex[1]);
+ rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~0x08000000;
+ }
+ }
-/*
- also tests for higher texunits:
+ /* maybe needs to be done pairwise due to 2 parallel (physical) tex units ?
+ looks like that's not the case, if 8500/9100 owners don't complain remove this...
+ for ( i = 0; i < ctx->Const.MaxTextureUnits; i += 2) {
+ if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ((R200_TEX_0_ENABLE |
+ R200_TEX_1_ENABLE ) << i)) == (R200_TEX_0_ENABLE << i)) &&
+ ((rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK) >
+ R200_MIN_FILTER_LINEAR)) {
+ R200_STATECHANGE(rmesa, ctx);
+ R200_STATECHANGE(rmesa, tex[i+1]);
+ rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= (R200_TEX_1_ENABLE << i);
+ rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
+ rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] |= 0x08000000;
+ }
+ else {
+ if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_1_ENABLE << i)) &&
+ (rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] & 0x08000000)) {
+ R200_STATECHANGE(rmesa, tex[i+1]);
+ rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] &= ~0x08000000;
+ }
+ }
+ } */
- ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_2_ENABLE) &&
- ((((rmesa->hw.tex[2].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & 0x04) == 0)) ||
- ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_4_ENABLE) &&
- ((((rmesa->hw.tex[4].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & 0x04) == 0)))
+ /*
+ * Texture cache LRU hang workaround -------------
+ * not needed for r200 derivatives?
+ */
+ dbg = 0x0;
+
+ if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_0_ENABLE )) &&
+ ((((rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
+ 0x04) == 0)) ||
+ ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_2_ENABLE) &&
+ ((((rmesa->hw.tex[2].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
+ 0x04) == 0)) ||
+ ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_4_ENABLE) &&
+ ((((rmesa->hw.tex[4].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
+ 0x04) == 0)))
+ {
+ dbg |= 0x02;
+ }
- ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_3_ENABLE) &&
- ((((rmesa->hw.tex[3].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & 0x04) == 0)) ||
- ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_5_ENABLE) &&
- ((((rmesa->hw.tex[5].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & 0x04) == 0)))
+ if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_1_ENABLE )) &&
+ ((((rmesa->hw.tex[1].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
+ 0x04) == 0)) ||
+ ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_3_ENABLE) &&
+ ((((rmesa->hw.tex[3].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
+ 0x04) == 0)) ||
+ ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_5_ENABLE) &&
+ ((((rmesa->hw.tex[5].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) &
+ 0x04) == 0)))
+ {
+ dbg |= 0x04;
+ }
-*/
+ if (dbg != rmesa->hw.tam.cmd[TAM_DEBUG3]) {
+ R200_STATECHANGE( rmesa, tam );
+ rmesa->hw.tam.cmd[TAM_DEBUG3] = dbg;
+ if (0) printf("TEXCACHE LRU HANG WORKAROUND %x\n", dbg);
+ }
+ }
+}
* memory. Could also use the counter/notify mechanism to populate
* tmp on the fly as vertices are generated.
*/
-static GLuint copy_dma_verts( r200ContextPtr rmesa, GLfloat (*tmp)[15] )
+static GLuint copy_dma_verts( r200ContextPtr rmesa, GLfloat (*tmp)[R200_MAX_VERTEX_SIZE] )
{
GLuint ovf, i;
GLuint nr = (rmesa->vb.initial_counter - rmesa->vb.counter) -
{
GET_CURRENT_CONTEXT(ctx);
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- GLfloat tmp[3][15];
+ GLfloat tmp[3][R200_MAX_VERTEX_SIZE];
GLuint i, prim;
GLuint ind0 = rmesa->vb.vtxfmt_0;
GLuint ind1 = rmesa->vb.vtxfmt_1;
offset++;
}
- count = VTX_TEXn_COUNT( ind1, 0 );
- dispatch_texcoord( count, &tmp[i][offset] );
- offset += count;
-
- for ( unit = 1 ; unit < ctx->Const.MaxTextureUnits ; unit++ ) {
+ for ( unit = 0 ; unit < ctx->Const.MaxTextureUnits ; unit++ ) {
count = VTX_TEXn_COUNT( ind1, unit );
dispatch_multitexcoord( count, unit, &tmp[i][offset] );
offset += count;
rmesa->vb.specptr->green,
rmesa->vb.specptr->blue );
- count = VTX_TEXn_COUNT( ind1, 0 );
- dispatch_texcoord( count, rmesa->vb.texcoordptr[0] );
-
- for ( unit = 1 ; unit < ctx->Const.MaxTextureUnits ; unit++ ) {
+ for ( unit = 0 ; unit < ctx->Const.MaxTextureUnits ; unit++ ) {
count = VTX_TEXn_COUNT( ind1, unit );
dispatch_multitexcoord( count, unit, rmesa->vb.texcoordptr[unit] );
}
{
GET_CURRENT_CONTEXT(ctx);
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- GLfloat tmp[3][15];
+ GLfloat tmp[3][R200_MAX_VERTEX_SIZE];
GLuint i, nrverts;
if (R200_DEBUG & (DEBUG_VFMT|DEBUG_PRIMS))
rmesa->vb.floatspecptr = ctx->Current.Attrib[VERT_ATTRIB_COLOR1];
rmesa->vb.texcoordptr[0] = ctx->Current.Attrib[VERT_ATTRIB_TEX0];
rmesa->vb.texcoordptr[1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1];
+ rmesa->vb.texcoordptr[2] = ctx->Current.Attrib[VERT_ATTRIB_TEX2];
+ rmesa->vb.texcoordptr[3] = ctx->Current.Attrib[VERT_ATTRIB_TEX3];
+ rmesa->vb.texcoordptr[4] = ctx->Current.Attrib[VERT_ATTRIB_TEX4];
+ rmesa->vb.texcoordptr[5] = ctx->Current.Attrib[VERT_ATTRIB_TEX5];
+ rmesa->vb.texcoordptr[6] = ctx->Current.Attrib[VERT_ATTRIB_TEX0]; /* dummy */
+ rmesa->vb.texcoordptr[7] = ctx->Current.Attrib[VERT_ATTRIB_TEX0]; /* dummy */
/* Run through and initialize the vertex components in the order
* the hardware understands:
* \c target before masking and using it. The value of GL_TEXTURE0 is 0x84C0,
* which has the low-order 5 bits 0. For all possible valid values of
* \c target. Subtracting GL_TEXTURE0 has the net effect of masking \c target
- * with 0x1F. Masking with 0x1F and then masking with 0x01 is redundant, so
+ * with 0x1F. Masking with 0x1F and then masking with 0x07 is redundant, so
* the subtraction has been omitted.
*/
} \
}
-MTEX_to_nF( 1f, (GLenum target, GLfloat s), (target & 1), s, 0.0, 0.0 )
-MTEX_to_nF( 2f, (GLenum target, GLfloat s, GLfloat t), (target & 1), s, t, 0.0 )
-MTEX_to_nF( 3f, (GLenum target, GLfloat s, GLfloat t, GLfloat r), (target & 1), s, t, r )
+/* \todo maybe (target & 4 ? target & 5 : target & 3) is more save than (target & 7) */
+MTEX_to_nF( 1f, (GLenum target, GLfloat s), (target & 7), s, 0.0, 0.0 )
+MTEX_to_nF( 2f, (GLenum target, GLfloat s, GLfloat t), (target & 7), s, t, 0.0 )
+MTEX_to_nF( 3f, (GLenum target, GLfloat s, GLfloat t, GLfloat r), (target & 7), s, t, r )
-MTEX_to_nF( 1fv, (GLenum target, const GLfloat *v), (target & 1), v[0], 0.0, 0.0 )
-MTEX_to_nF( 2fv, (GLenum target, const GLfloat *v), (target & 1), v[0], v[1], 0.0 )
-MTEX_to_nF( 3fv, (GLenum target, const GLfloat *v), (target & 1), v[0], v[1], v[2] )
+MTEX_to_nF( 1fv, (GLenum target, const GLfloat *v), (target & 7), v[0], 0.0, 0.0 )
+MTEX_to_nF( 2fv, (GLenum target, const GLfloat *v), (target & 7), v[0], v[1], 0.0 )
+MTEX_to_nF( 3fv, (GLenum target, const GLfloat *v), (target & 7), v[0], v[1], v[2] )
static struct dynfn *lookup( struct dynfn *l, const int *key )
{
/* VTXFMT_1
*/
#define MASK_ST0 (0x7 << R200_VTX_TEX0_COMP_CNT_SHIFT)
-
+/* FIXME: maybe something like in the radeon driver is needed here? */
typedef void (*p4f)( GLfloat, GLfloat, GLfloat, GLfloat );
GLOBL( _x86_Color4ub_ub_end )
+/* \todo: change the "and $7, %eax" to something like "target & 4 ? target & 5 : target & 3)" */
/*
MultiTexCoord2fv st0/st1
*/
GLOBL( _x86_MultiTexCoord2fv )
movl 4(%esp), %eax
movl 8(%esp), %ecx
- and $1, %eax
+ and $7, %eax
movl (%ecx), %edx
shl $3, %eax
movl 4(%ecx), %ecx
GLOBL( _x86_MultiTexCoord2fv_2 )
movl 4(%esp,1), %eax
movl 8(%esp,1), %ecx
- and $0x1, %eax
+ and $0x7, %eax
movl 0(,%eax,4), %edx
movl (%ecx), %eax
movl %eax, (%edx)
movl 4(%esp), %eax
movl 8(%esp), %edx
movl 12(%esp), %ecx
- and $1, %eax
+ and $7, %eax
shl $3, %eax
movl %edx, 0xdeadbeef(%eax)
movl %ecx, 0xdeadbeef(%eax)
movl 4(%esp), %eax
movl 8(%esp), %edx
movl 12(%esp,1), %ecx
- and $1,%eax
+ and $7,%eax
movl 0(,%eax,4), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
GLOBL( _sse_MultiTexCoord2fv )
movl 4(%esp), %eax
movl 8(%esp), %ecx
- and $1, %eax
+ and $7, %eax
movlps (%ecx), %xmm0
movlps %xmm0, 0xdeadbeef(,%eax,8)
ret
GLOBL( _sse_MultiTexCoord2fv_2 )
movl 4(%esp), %eax
movl 8(%esp), %ecx
- and $0x1, %eax
+ and $0x7, %eax
movl 0(,%eax,4), %edx
movlps (%ecx), %xmm0
movlps %xmm0, (%edx)
*/
GLOBL( _sse_MultiTexCoord2f )
movl 4(%esp), %eax
- and $1, %eax
+ and $7, %eax
movlps 8(%esp), %xmm0
movlps %xmm0, 0xdeadbeef(,%eax,8)
ret
GLOBL( _sse_MultiTexCoord2f_2 )
movl 4(%esp), %eax
movlps 8(%esp), %xmm0
- and $1,%eax
+ and $7,%eax
movl 0(,%eax,4), %eax
movlps %xmm0, (%eax)
ret
projects / mesa.git / commitdiff