(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e16f700f8eca358eaafa868553319bd9cf024b8d..f7117b08eb64b54ecb2a056a85f86a026077a106 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -49,6 +49,16 @@ Advantages of these design principles:
   but off of Vectorisation ISAs as well.  No more separate Vector
   instructions.
 
+Comparative instruction count:
+
+* ARM NEON SIMD: around 2,000 instructions, prerequisite: ARM Scalar.
+* ARM SVE: around 4,000 instructions, prerequisite: NEON. 
+* ARM SVE2: around 1,000 instructions, prerequisite: SVE
+* Intel AVX-512: around 4,000 instructions, prerequisite AVX2 etc.
+* RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
+* SVP64: **four** instructions, prerequisite SFS (150) or
+  SFFS (214) Compliancy Subsets
+
 # Major opcodes summary
 
 Please be advised that even though below is entirely DRAFT status, there