+2019-09-16 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/91719
+ * config/i386/i386.h (TARGET_USE_XCHG_FOR_ATOMIC_STORE): New macro.
+ * config/i386/x86-tune.def (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE): New.
+ * config/i386/sync.md (atomic_store<mode>): emit XCHG for
+ TARGET_USE_XCHG_FOR_ATOMIC_STORE.
+
2019-09-16 Jason Merrill <jason@redhat.com>
* Makefile.in (build/genmatch.o): Depend on $(CPPLIB_H).
ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
#define TARGET_ONE_IF_CONV_INSN \
ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
+#define TARGET_USE_XCHG_FOR_ATOMIC_STORE \
+ ix86_tune_features[X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE]
#define TARGET_EMIT_VZEROUPPER \
ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
{
operands[1] = force_reg (<MODE>mode, operands[1]);
- /* For seq-cst stores, when we lack MFENCE, use XCHG. */
- if (is_mm_seq_cst (model) && !(TARGET_64BIT || TARGET_SSE2))
+ /* For seq-cst stores, use XCHG
+ when we lack MFENCE or when target prefers XCHG. */
+ if (is_mm_seq_cst (model)
+ && (!(TARGET_64BIT || TARGET_SSE2)
+ || TARGET_USE_XCHG_FOR_ATOMIC_STORE))
{
emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode),
operands[0], operands[1],
m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
+/* X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE: Use xchg instead of mov+mfence. */
+DEF_TUNE (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE, "use_xchg_for_atomic_store",
+ m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
+
/*****************************************************************************/
/* 387 instruction selection tuning */
/*****************************************************************************/