Add build Makefile and JTAG load script

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..9ebc706
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,32 @@
+PYTHON=python3
+
+all: build/soc.bit
+
+# We need to change to the build directory because the Xilinx tools
+# tend to dump a mess of various files in the current directory.
+
+build/soc.prj build/soc.ucf:
+       $(PYTHON) build.py
+
+build/soc.ngc: build/soc.prj
+       cd build && xst -ifn ../soc.xst
+
+build/soc.ngd: build/soc.ngc build/soc.ucf
+       cd build && ngdbuild -uc soc.ucf soc.ngc
+
+build/soc.ncd: build/soc.ngd
+       cd build && map -ol high -w soc.ngd
+
+build/soc-routed.ncd: build/soc.ncd
+       cd build && par -ol high -w soc.ncd soc-routed.ncd
+
+build/soc.bit build/soc.bin: build/soc-routed.ncd
+       cd build && bitgen -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit
+
+load: build/soc.bit
+       jtag -n load.jtag
+
+clean:
+       rm -rf build/*
+
+.PHONY: load clean

diff --git a/build.py b/build.py
index aaf9c569d2ecfee7bec3b979c81926e0304758f6..a9ee5aae3cceb75b63ea436dee4c3c3448106d0b 100644 (file)
--- a/build.py
+++ b/build.py
@@ -21,7 +21,6 @@ add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v
        "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
        "jtag_tap_spartan6.v"])
 
-os.system("rm -rf build/*")
 os.chdir("build")
 
 def str2file(filename, contents):
@@ -35,33 +34,8 @@ str2file("soc.v", src_verilog)
 str2file("soc.ucf", src_ucf)
 verilog_sources.append("build/soc.v")
 
-#raise SystemExit
-
-# xst
+# generate XST project file
 xst_prj = ""
 for s in verilog_sources:
        xst_prj += "verilog work ../" + s + "\n"
 str2file("soc.prj", xst_prj)
-str2file("soc.xst", """run
--ifn soc.prj
--top soc
--ifmt MIXED
--opt_mode SPEED
--opt_level 2
--resource_sharing no
--reduce_control_sets auto
--ofn soc.ngc
--p xc6slx45-fgg484-2""")
-os.system("xst -ifn soc.xst")
-
-# ngdbuild
-os.system("ngdbuild -uc soc.ucf soc.ngc")
-
-# map
-os.system("map -ol high -w soc.ngd")
-
-# par
-os.system("par -ol high -w soc.ncd soc-routed.ncd")
-
-# bitgen
-os.system("bitgen -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")

diff --git a/load.jtag b/load.jtag
new file mode 100644 (file)
index 0000000..8fbe562
--- /dev/null
+++ b/load.jtag
@@ -0,0 +1,5 @@
+cable milkymist
+detect
+instruction CFG_OUT  000100 BYPASS
+instruction CFG_IN   000101 BYPASS
+pld load build/soc.bit

diff --git a/soc.xst b/soc.xst
new file mode 100644 (file)
index 0000000..7162d23
--- /dev/null
+++ b/soc.xst
@@ -0,0 +1,10 @@
+run
+-ifn soc.prj
+-top soc
+-ifmt MIXED
+-opt_mode SPEED
+-opt_level 2
+-resource_sharing no
+-reduce_control_sets auto
+-ofn soc.ngc
+-p xc6slx45-fgg484-2