Multiply needs to be 16 stages to fix all timing issues

This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/multiply.vhdl b/multiply.vhdl
index 6f80660da914b2feac0eee8831d2d6efd599c922..71aceca8ad553dde48969382fee6c07727621d03 100644 (file)
--- a/multiply.vhdl
+++ b/multiply.vhdl
@@ -10,7 +10,7 @@ use work.crhelpers.all;
 
 entity multiply is
     generic (
-        PIPELINE_DEPTH : natural := 2
+        PIPELINE_DEPTH : natural := 16
         );
     port (
         clk   : in std_logic;