split out instructions from openpower/isa/fixedtrap.mdwn

diff --git a/openpower/isa/fixedtrap.mdwn b/openpower/isa/fixedtrap.mdwn
index 9e9df5794725f6631f70146e5d9d3113c1d00d44..11d80ef5333e3cb0ea8e571d71158dd992aab403 100644 (file)
--- a/openpower/isa/fixedtrap.mdwn
+++ b/openpower/isa/fixedtrap.mdwn
@@ -7,98 +7,12 @@
 <!-- handler is invoked. If none of the tested conditions are met, instruction -->
 <!-- execution continues normally. -->
 
-# Trap Word Immediate
+[[!inline pagenames="openpower/isa/fixedtrap/twi" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedtrap/tw" raw="yes"]]
 
-* twi TO,RA,SI
+[[!inline pagenames="openpower/isa/fixedtrap/tdi" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedtrap/td" raw="yes"]]
 
-    a <- EXTS((RA)[XLEN/2:XLEN-1])
-    if (a < EXTS(SI)) & TO[0]  then TRAP
-    if (a > EXTS(SI)) & TO[1]  then TRAP
-    if (a = EXTS(SI)) & TO[2]  then TRAP
-    if (a <u EXTS(SI)) & TO[3] then TRAP
-    if (a >u EXTS(SI)) & TO[4] then TRAP
-
-Special Registers Altered:
-
-    None
-
-# Trap Word
-
-X-Form
-
-* tw TO,RA,RB
-
-Pseudo-code:
-
-    a <- EXTS((RA)[XLEN/2:XLEN-1])
-    b <- EXTS((RB)[XLEN/2:XLEN-1])
-    if (a < b) & TO[0] then TRAP
-    if (a > b) & TO[1] then TRAP
-    if (a = b) & TO[2] then TRAP
-    if (a <u b) & TO[3] then TRAP
-    if (a >u b) & TO[4] then TRAP
-
-Special Registers Altered:
-
-    None
-
-# Trap Doubleword Immediate
-
-D-Form
-
-* tdi TO,RA,SI
-
-Pseudo-code:
-
-    a <- (RA)
-    b <- EXTS(SI)
-    if (a < b) & TO[0] then TRAP
-    if (a > b) & TO[1] then TRAP
-    if (a = b) & TO[2] then TRAP
-    if (a <u  b) & TO[3] then TRAP
-    if (a >u  b) & TO[4]  then TRAP
-
-Special Registers Altered:
-
-    None
-
-# Trap Doubleword
-
-X-Form
-
-* td TO,RA,RB
-
-Pseudo-code:
-
-    a <- (RA)
-    b <- (RB)
-    if (a < b) & TO[0] then TRAP
-    if (a > b) & TO[1] then TRAP
-    if (a = b) & TO[2] then TRAP
-    if (a <u b) & TO[3] then TRAP
-    if (a >u b) & TO[4]  then TRAP
-
-Special Registers Altered:
-
-    None
-
-# Integer Select
-
-A-Form
-
-* isel RT,RA,RB,BC
-
-Pseudo-code:
-
-    if CR[BC+32]=1 then RT <- (RA|0)
-    else                RT <- (RB)
-
-Special Registers Altered:
-
-    None
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/fixedtrap/isel" raw="yes"]]

diff --git a/openpower/isa/fixedtrap/isel.mdwn b/openpower/isa/fixedtrap/isel.mdwn
new file mode 100644 (file)
index 0000000..6eeae64
--- /dev/null
+++ b/openpower/isa/fixedtrap/isel.mdwn
@@ -0,0 +1,15 @@
+# Integer Select
+
+A-Form
+
+* isel RT,RA,RB,BC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedtrap/isel_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Checked March 2021 -->

diff --git a/openpower/isa/fixedtrap/isel_code.mdwn b/openpower/isa/fixedtrap/isel_code.mdwn
new file mode 100644 (file)
index 0000000..43b1d11
--- /dev/null
+++ b/openpower/isa/fixedtrap/isel_code.mdwn
@@ -0,0 +1,2 @@
+    if CR[BC+32]=1 then RT <- (RA|0)
+    else                RT <- (RB)

diff --git a/openpower/isa/fixedtrap/td.mdwn b/openpower/isa/fixedtrap/td.mdwn
new file mode 100644 (file)
index 0000000..61a2c87
--- /dev/null
+++ b/openpower/isa/fixedtrap/td.mdwn
@@ -0,0 +1,13 @@
+# Trap Doubleword
+
+X-Form
+
+* td TO,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedtrap/td_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedtrap/td_code.mdwn b/openpower/isa/fixedtrap/td_code.mdwn
new file mode 100644 (file)
index 0000000..a5fde46
--- /dev/null
+++ b/openpower/isa/fixedtrap/td_code.mdwn
@@ -0,0 +1,7 @@
+    a <- (RA)
+    b <- (RB)
+    if (a < b) & TO[0] then TRAP
+    if (a > b) & TO[1] then TRAP
+    if (a = b) & TO[2] then TRAP
+    if (a <u b) & TO[3] then TRAP
+    if (a >u b) & TO[4]  then TRAP

diff --git a/openpower/isa/fixedtrap/tdi.mdwn b/openpower/isa/fixedtrap/tdi.mdwn
new file mode 100644 (file)
index 0000000..9642559
--- /dev/null
+++ b/openpower/isa/fixedtrap/tdi.mdwn
@@ -0,0 +1,13 @@
+# Trap Doubleword Immediate
+
+D-Form
+
+* tdi TO,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedtrap/tdi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedtrap/tdi_code.mdwn b/openpower/isa/fixedtrap/tdi_code.mdwn
new file mode 100644 (file)
index 0000000..5de8553
--- /dev/null
+++ b/openpower/isa/fixedtrap/tdi_code.mdwn
@@ -0,0 +1,7 @@
+    a <- (RA)
+    b <- EXTS(SI)
+    if (a < b) & TO[0] then TRAP
+    if (a > b) & TO[1] then TRAP
+    if (a = b) & TO[2] then TRAP
+    if (a <u  b) & TO[3] then TRAP
+    if (a >u  b) & TO[4]  then TRAP

diff --git a/openpower/isa/fixedtrap/tw.mdwn b/openpower/isa/fixedtrap/tw.mdwn
new file mode 100644 (file)
index 0000000..2dbb189
--- /dev/null
+++ b/openpower/isa/fixedtrap/tw.mdwn
@@ -0,0 +1,13 @@
+# Trap Word
+
+X-Form
+
+* tw TO,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedtrap/tw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedtrap/tw_code.mdwn b/openpower/isa/fixedtrap/tw_code.mdwn
new file mode 100644 (file)
index 0000000..b7309e5
--- /dev/null
+++ b/openpower/isa/fixedtrap/tw_code.mdwn
@@ -0,0 +1,7 @@
+    a <- EXTS((RA)[XLEN/2:XLEN-1])
+    b <- EXTS((RB)[XLEN/2:XLEN-1])
+    if (a < b) & TO[0] then TRAP
+    if (a > b) & TO[1] then TRAP
+    if (a = b) & TO[2] then TRAP
+    if (a <u b) & TO[3] then TRAP
+    if (a >u b) & TO[4] then TRAP

diff --git a/openpower/isa/fixedtrap/twi.mdwn b/openpower/isa/fixedtrap/twi.mdwn
new file mode 100644 (file)
index 0000000..d5571a4
--- /dev/null
+++ b/openpower/isa/fixedtrap/twi.mdwn
@@ -0,0 +1,13 @@
+# Trap Word Immediate
+
+D-Form
+
+* twi TO,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedtrap/twi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedtrap/twi_code.mdwn b/openpower/isa/fixedtrap/twi_code.mdwn
new file mode 100644 (file)
index 0000000..abd1056
--- /dev/null
+++ b/openpower/isa/fixedtrap/twi_code.mdwn
@@ -0,0 +1,6 @@
+    a <- EXTS((RA)[XLEN/2:XLEN-1])
+    if (a < EXTS(SI)) & TO[0]  then TRAP
+    if (a > EXTS(SI)) & TO[1]  then TRAP
+    if (a = EXTS(SI)) & TO[2]  then TRAP
+    if (a <u EXTS(SI)) & TO[3] then TRAP
+    if (a >u EXTS(SI)) & TO[4] then TRAP