sparc.h (FIXED_REGISTERS): Add %icc.

	* config/sparc/sparc.h (FIXED_REGISTERS): Add %icc.

	* config/visium/visium.c (visium_expand_int_cstore): Revert latest
	change.
	(visium_expand_fp_cstore): Likewise.

From-SVN: r240892

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 92ea9a3f39dc2f5f84b5a2bb504190619ec6d8ed..6efa7379a2287bee8b6edddab9098c3ccbaf3ae1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-10-08  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * config/sparc/sparc.h (FIXED_REGISTERS): Add %icc.
+
+       * config/visium/visium.c (visium_expand_int_cstore): Revert latest
+       change.
+       (visium_expand_fp_cstore): Likewise.
+
 2016-10-08  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
 
        * diagnostic-core.h (warning_at_rich_loc_n): Declare.

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index d91496ab6abb7f21ac06456b4ead25b873749ea5..4674c30125e36c1a2f347f1ae930bcc904a55ffc 100644 (file)
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -603,7 +603,8 @@ extern enum cmodel sparc_cmodel;
    (e.g.: in CLASS_MAX_NREGS).  There are also 4 fp condition code registers, so
    32+32+32+4 == 100.
    Register 100 is used as the integer condition code register.
-   Register 101 is used as the soft frame pointer register.  */
+   Register 101 is used as the soft frame pointer register.
+   Register 102 is used as the general status register by VIS instructions.  */
 
 #define FIRST_PSEUDO_REGISTER 103
 
@@ -678,7 +679,7 @@ extern enum cmodel sparc_cmodel;
   0, 0, 0, 0, 0, 0, 0, 0,      \
   0, 0, 0, 0, 0, 0, 0, 0,      \
                                \
-  0, 0, 0, 0, 0, 1, 1}
+  0, 0, 0, 0, 1, 1, 1}
 
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
@@ -885,12 +886,7 @@ extern int sparc_mode_class[];
    have a class that is the union of FPCC_REGS with either of the others,
    it is important that it appear first.  Otherwise the compiler will die
    trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
-   constraints.
-
-   It is important that SPARC_ICC_REG have class NO_REGS.  Otherwise combine
-   may try to use it to hold an SImode value.  See register_operand.
-   ??? Should %fcc[0123] be handled similarly?
-*/
+   constraints.  */
 
 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
                 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,

diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 3ce79f4d5c85a24d3fcd2ce4b3dcc95c4528b99d..af58f99aef1ea60710ef5e0527ac3417d1921dc5 100644 (file)
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -2222,7 +2222,7 @@ visium_expand_int_cstore (rtx *operands, enum machine_mode mode)
       code = reverse_condition (code);
       reverse = true;
 
-      /* fall through */
+      /* ... fall through ...  */
 
     case LTU:
     case GTU:
@@ -2270,7 +2270,7 @@ visium_expand_fp_cstore (rtx *operands,
       code = reverse_condition_maybe_unordered (code);
       reverse = true;
 
-      /* fall through */
+      /* ... fall through ...  */
 
     case LT:
     case GT: