S/390: Increase latencies for some FP instructions

This patch increases the latency of some floating point instructions to better
match the real machine's behavior.

2018-10-08  Robin Dapp  <rdapp@linux.ibm.com>

	* config/s390/2827.md: Increase latencies for some FP instructions.

From-SVN: r264927

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b7265c0236ed71cdcf412329ca325865dc9783e1..1ee5edde975eeaf48874072aab5f8f79076ac830 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2018-10-08  Robin Dapp  <rdapp@linux.ibm.com>
+
+       * config/s390/2827.md: Increase latencies for some FP instructions.
+
 2018-10-08  Richard Biener  <rguenther@suse.de>
 
        * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):

diff --git a/gcc/config/s390/2827.md b/gcc/config/s390/2827.md
index a709a2e9f46bbf3a82e646a9aadbc1f1048d8bce..1fef0bbb59734e2c3f7c45ea61a9ea83b0be8744 100644 (file)
--- a/gcc/config/s390/2827.md
+++ b/gcc/config/s390/2827.md
@@ -38,9 +38,13 @@
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "ltg,ogrk,lr,lghrl,x,asi,lhr,ar,lhrl,llgfr,clghrl,cgr,cli,agrk,ic,lrv,clg,cy,cghi,sy,clgfr,al,tm,lang,lghr,laa,ark,lh,or,icy,xi,n,llihl,afi,cs,nrk,sth,lgr,l,lcr,stey,xg,crt,slgfr,ny,ld,j,llihh,slgr,clfhsi,slg,lb,lgrl,lrl,llihf,llcr,laxg,mvghi,rllg,xrk,laag,alhsik,algfi,algr,aly,agfi,lrvr,d,crl,llgc,tmhl,algsi,lgh,icmh,clhrl,xgrk,icm,iilf,ork,cg,ldgr,lgf,iihf,llghr,sg,stam,tmhh,slgf,basr,lgb,cgfi,lax,clfit,lrvgr,nihl,ni,srdl,srk,xihf,stgrl,sthrl,algf,cgit,ng,lat,llghrl,ltgr,nihh,clgfrl,srlk,agr,ler,bcr_flush,stcy,cds,clfi,nihf,ly,clt,lgat,alg,lhy,lgfrl,clghsi,clrt,tmll,srlg,ay,sty,clr,lgfi,lan,clgt,ahik,sra,algrk,clgr,tmy,tmlh,alghsik,lcgr,mvi,ltgf,xr,larl,ldr,llgcr,clgrt,clrl,cghsi,cliy,oy,ogr,llgt,slr,chi,s,icmy,llc,ngr,clhhsi,ltgfr,llill,lhi,o,sll,clgrl,clgf,mviy,algfr,rll,sldl,lg,niy,st,sgr,ag,le,xgr,cr,stg,llilh,sr,cdsg,sllk,stoc,csg,clgit,chhsi,strl,llilf,lndfr,ngrk,clgfi,llgh,oill,la,llhrl,stc,lghi,oihl,xiy,sllg,llgf,cgrt,cl,sl,oi,oilh,nr,srak,oihh,ear,slgrk,og,c,slgfi,sthy,oilf,oiy,oihf,a,cfi,srag,brasl,alr,cgrl,llgfrl,cit,ley,exrl,lcdfr,lay,xilf,alsi,mvhhi,srl,chsi,lgfr,lrvg,cly,sgrk,ahi,nill,jg,slrk,lxr,sar,slfi,cpsdr,lcgfr,aghik,nilh,mvhi,lpdfr,xy,alrk,lao,agsi,ldy,nilf,llhr,alfi,laog,sly,aghi,bras,srda,lt,lbr,lzxr,lzdr,lzer")) "nothing")
 
-(define_insn_reservation "zEC12_simple_fp" 1
+(define_insn_reservation "zEC12_simple_fp" 0
   (and (eq_attr "cpu" "zEC12")
-       (eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,llgtr,cebr,lgbr,maebr,ltebr,clfdtr,ltr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,fixbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb")) "nothing")
+       (eq_attr "mnemonic" "llgtr,lgbr,ltr")) "nothing")
+
+(define_insn_reservation "zEC12_normal_fp" 8
+  (and (eq_attr "cpu" "zEC12")
+       (eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,cebr,maebr,ltebr,clfdtr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb")) "nothing")
 
 (define_insn_reservation "zEC12_cgdbr" 2
   (and (eq_attr "cpu" "zEC12")
@@ -294,7 +298,7 @@
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "locgr")) "nothing")
 
-(define_insn_reservation "zEC12_debr" 23
+(define_insn_reservation "zEC12_debr" 29
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "debr")) "nothing")
 
@@ -422,7 +426,7 @@
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "cxbr")) "nothing")
 
-(define_insn_reservation "zEC12_ddbr" 30
+(define_insn_reservation "zEC12_ddbr" 36
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "ddbr")) "nothing")
 
@@ -430,7 +434,7 @@
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "stmy")) "nothing")
 
-(define_insn_reservation "zEC12_ste" 3
+(define_insn_reservation "zEC12_ste" 4
   (and (eq_attr "cpu" "zEC12")
        (eq_attr "mnemonic" "ste")) "nothing")