namespace detail
{
-struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, const RTLIL::SigBit *> {
+struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, RTLIL::SigBit> {
using set_iter_t = std::set<RTLIL::SigBit>::iterator;
const Netlist &net;
- const RTLIL::SigBit *p_sig;
+ RTLIL::SigBit sig;
+ bool sentinel;
+
std::stack<std::pair<set_iter_t, set_iter_t>> dfs_path_stack;
std::set<RTLIL::Cell *> cells_visited;
- NetlistConeWireIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig) {}
+ NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true) {}
+
+ NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig), sentinel(false) {}
- const RTLIL::SigBit &operator*() const { return *p_sig; };
- bool operator!=(const NetlistConeWireIter &other) const { return p_sig != other.p_sig; }
- bool operator==(const NetlistConeWireIter &other) const { return p_sig == other.p_sig; }
+ const RTLIL::SigBit &operator*() const { return sig; };
+ bool operator!=(const NetlistConeWireIter &other) const
+ {
+ if (sentinel || other.sentinel) {
+ return sentinel != other.sentinel;
+ } else {
+ return sig != other.sig;
+ }
+ }
+
+ bool operator==(const NetlistConeWireIter &other) const {
+ if (sentinel || other.sentinel) {
+ return sentinel == other.sentinel;
+ } else {
+ return sig == other.sig;
+ }
+ }
void next_sig_in_dag()
{
while (1) {
if (dfs_path_stack.empty()) {
- p_sig = NULL;
+ sentinel = true;
return;
}
cell_inputs_iter++;
if (cell_inputs_iter != cell_inputs_iter_guard) {
- p_sig = &(*cell_inputs_iter);
+ sig = *cell_inputs_iter;
return;
} else {
dfs_path_stack.pop();
NetlistConeWireIter &operator++()
{
- if (net.sigbit_driver_map.count(*p_sig)) {
- auto drv = net.sigbit_driver_map.at(*p_sig);
+ if (net.sigbit_driver_map.count(sig)) {
+ auto drv = net.sigbit_driver_map.at(sig);
if (!cells_visited.count(drv)) {
auto &inputs = net.cell_inputs_map.at(drv);
dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end()));
cells_visited.insert(drv);
- p_sig = &(*dfs_path_stack.top().first);
+ sig = (*dfs_path_stack.top().first);
} else {
next_sig_in_dag();
}
struct NetlistConeWireIterable {
const Netlist &net;
- const RTLIL::SigBit *p_sig;
+ RTLIL::SigBit sig;
- NetlistConeWireIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
+ NetlistConeWireIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
- NetlistConeWireIter begin() { return NetlistConeWireIter(net, p_sig); }
+ NetlistConeWireIter begin() { return NetlistConeWireIter(net, sig); }
NetlistConeWireIter end() { return NetlistConeWireIter(net); }
};
-struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
+struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, RTLIL::Cell *> {
const Netlist &net;
- const RTLIL::SigBit *p_sig;
NetlistConeWireIter sig_iter;
- NetlistConeCellIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig)
+ NetlistConeCellIter(const Netlist &net) : net(net), sig_iter(net) {}
+
+ NetlistConeCellIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig_iter(net, sig)
{
- if ((p_sig != NULL) && (!has_driver_cell(*sig_iter))) {
+ if ((!sig_iter.sentinel) && (!has_driver_cell(*sig_iter))) {
++(*this);
}
}
{
while (true) {
++sig_iter;
- if (sig_iter.p_sig == NULL) {
+ if (sig_iter.sentinel) {
return *this;
}
struct NetlistConeCellIterable {
const Netlist &net;
- const RTLIL::SigBit *p_sig;
+ RTLIL::SigBit sig;
- NetlistConeCellIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
+ NetlistConeCellIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
- NetlistConeCellIter begin() { return NetlistConeCellIter(net, p_sig); }
+ NetlistConeCellIter begin() { return NetlistConeCellIter(net, sig); }
NetlistConeCellIter end() { return NetlistConeCellIter(net); }
};
-struct NetlistConeInputsIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
- const Netlist &net;
- const RTLIL::SigBit *p_sig;
-
- NetlistConeWireIter sig_iter;
-
- bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
-
- NetlistConeInputsIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig)
- {
- if ((p_sig != NULL) && (has_driver_cell(*sig_iter))) {
- ++(*this);
- }
- }
-
- const RTLIL::SigBit &operator*() const { return *sig_iter; };
- bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; }
- bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; }
- NetlistConeInputsIter &operator++()
- {
- do {
- ++sig_iter;
- if (sig_iter.p_sig == NULL) {
- return *this;
- }
- } while (has_driver_cell(*sig_iter));
-
- return *this;
- }
-};
-
-struct NetlistConeInputsIterable {
- const Netlist &net;
- const RTLIL::SigBit *p_sig;
-
- NetlistConeInputsIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
-
- NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, p_sig); }
- NetlistConeInputsIter end() { return NetlistConeInputsIter(net); }
-};
+// struct NetlistConeInputsIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
+// const Netlist &net;
+// RTLIL::SigBit sig;
+
+// NetlistConeWireIter sig_iter;
+
+// bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
+
+// NetlistConeInputsIter(const Netlist &net, RTLIL::SigBit sig = NULL) : net(net), sig(sig), sig_iter(net, sig)
+// {
+// if ((sig != NULL) && (has_driver_cell(sig_iter))) {
+// ++(*this);
+// }
+// }
+
+// const RTLIL::SigBit &operator*() const { return sig_iter; };
+// bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; }
+// bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; }
+// NetlistConeInputsIter &operator++()
+// {
+// do {
+// ++sig_iter;
+// if (sig_iter->empty()) {
+// return *this;
+// }
+// } while (has_driver_cell(sig_iter));
+
+// return *this;
+// }
+// };
+
+// struct NetlistConeInputsIterable {
+// const Netlist &net;
+// RTLIL::SigBit sig;
+
+// NetlistConeInputsIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
+
+// NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, sig); }
+// NetlistConeInputsIter end() { return NetlistConeInputsIter(net); }
+// };
} // namespace detail
-detail::NetlistConeWireIterable cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeWireIterable(net, &sig); }
+detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeWireIterable(net, net.sigmap(sig)); }
-// detail::NetlistConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return NetlistConeInputsIterable(this, &sig); }
-detail::NetlistConeCellIterable cell_cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeCellIterable(net, &sig); }
+// detail::NetlistConeInputsIterable cone_inputs(RTLIL::SigBit sig) { return NetlistConeInputsIterable(this, &sig); }
+detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeCellIterable(net, net.sigmap(sig)); }
YOSYS_NAMESPACE_END