--- /dev/null
+<!-- Transcendental FP Instructions -->
+
+<!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
+
+# [DRAFT] Floating SIN [Single]
+
+X-Form
+
+* fsins FRT,FRB (Rc=0)
+* fsins. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+ FRT <- FPSIN32(FRB)
+
+Special Registers Altered:
+
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI VXIMZ
+ CR1 (if Rc=1)
+
+# [DRAFT] Floating COS [Single]
+
+X-Form
+
+* fcoss FRT,FRB (Rc=0)
+* fcoss. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+ FRT <- FPCOS32(FRB)
+
+Special Registers Altered:
+
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI VXIMZ
+ CR1 (if Rc=1)
+
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-
-# [DRAFT] Floating SIN [Single]
-
-X-Form
-
-* fsins FRT,FRB (Rc=0)
-* fsins. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
- FRT <- FPSIN32(FRB)
-
-Special Registers Altered:
-
- FPRF FR FI
- FX OX UX XX
- VXSNAN VXISI VXIMZ
- CR1 (if Rc=1)
-
-# [DRAFT] Floating COS [Single]
-
-X-Form
-
-* fcoss FRT,FRB (Rc=0)
-* fcoss. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
- FRT <- FPCOS32(FRB)
-
-Special Registers Altered:
-
- FPRF FR FI
- FX OX UX XX
- VXSNAN VXISI VXIMZ
- CR1 (if Rc=1)
-