boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/dist/m5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 10:28:58
-gem5 started Dec 4 2015 11:07:13
-gem5 executing on e104799-lin, pid 25873
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:39
+gem5 executing on zizzer, pid 26207
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
sim_ticks 1869358498000 # Number of ticks simulated
final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1636822 # Simulator instruction rate (inst/s)
-host_op_rate 1636821 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47073565091 # Simulator tick rate (ticks/s)
-host_mem_usage 332968 # Number of bytes of host memory used
-host_seconds 39.71 # Real time elapsed on the host
+host_inst_rate 926044 # Simulator instruction rate (inst/s)
+host_op_rate 926044 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26632227382 # Simulator tick rate (ticks/s)
+host_mem_usage 313988 # Number of bytes of host memory used
+host_seconds 70.19 # Real time elapsed on the host
sim_insts 65000470 # Number of instructions simulated
sim_ops 65000470 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/dist/m5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 10:28:58
-gem5 started Dec 4 2015 10:35:24
-gem5 executing on e104799-lin, pid 22025
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:28
+gem5 executing on zizzer, pid 26161
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332273500 because m5_exit instruction encountered
sim_ticks 1829332273500 # Number of ticks simulated
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1702079 # Simulator instruction rate (inst/s)
-host_op_rate 1702079 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51861293564 # Simulator tick rate (ticks/s)
-host_mem_usage 329640 # Number of bytes of host memory used
-host_seconds 35.27 # Real time elapsed on the host
+host_inst_rate 1025442 # Simulator instruction rate (inst/s)
+host_op_rate 1025441 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 31244562480 # Simulator tick rate (ticks/s)
+host_mem_usage 310964 # Number of bytes of host memory used
+host_seconds 58.55 # Real time elapsed on the host
sim_insts 60038341 # Number of instructions simulated
sim_ops 60038341 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/dist/m5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 10:28:58
-gem5 started Dec 4 2015 10:53:21
-gem5 executing on e104799-lin, pid 24287
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26155
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 881785000
sim_ticks 1982594146000 # Number of ticks simulated
final_tick 1982594146000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 876674 # Simulator instruction rate (inst/s)
-host_op_rate 876674 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28498337600 # Simulator tick rate (ticks/s)
-host_mem_usage 332972 # Number of bytes of host memory used
-host_seconds 69.57 # Real time elapsed on the host
+host_inst_rate 454315 # Simulator instruction rate (inst/s)
+host_op_rate 454314 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14768552865 # Simulator tick rate (ticks/s)
+host_mem_usage 314396 # Number of bytes of host memory used
+host_seconds 134.24 # Real time elapsed on the host
sim_insts 60989111 # Number of instructions simulated
sim_ops 60989111 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/dist/m5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 10:28:58
-gem5 started Dec 4 2015 10:54:46
-gem5 executing on e104799-lin, pid 24468
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:28
+gem5 executing on zizzer, pid 26167
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1941275996000 because m5_exit instruction encountered
sim_ticks 1941275996000 # Number of ticks simulated
final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 921196 # Simulator instruction rate (inst/s)
-host_op_rate 921196 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31829968739 # Simulator tick rate (ticks/s)
-host_mem_usage 330408 # Number of bytes of host memory used
-host_seconds 60.99 # Real time elapsed on the host
+host_inst_rate 457137 # Simulator instruction rate (inst/s)
+host_op_rate 457137 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15795402578 # Simulator tick rate (ticks/s)
+host_mem_usage 311136 # Number of bytes of host memory used
+host_seconds 122.90 # Real time elapsed on the host
sim_insts 56182743 # Number of instructions simulated
sim_ops 56182743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"highest_el_is_64": false,
- "kernel": "/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5",
+ "kernel": "/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5",
"iobus": {
"slave": {
"peer": [
"frontend_latency": 2
},
"symbolfile": "",
- "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh",
+ "readfile": "/z/atgutier/gem5/gem5/tests/halt.sh",
"have_large_asid_64": false,
"phys_addr_range_64": 40,
"have_lpae": false,
"multi_proc": true,
"early_kernel_symbols": false,
"panic_on_oops": true,
- "dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb",
+ "dtb_filename": "/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb",
"panic_on_panic": true,
"enable_context_switch_stats_dump": false,
"work_begin_ckpt_count": 0,
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.cf0.image.child",
- "image_file": "/work/gem5/dist/disks/linux-aarch32-ael.img",
+ "image_file": "/dist/m5/system/disks/linux-aarch32-ael.img",
"type": "RawDiskImage"
},
"path": "system.cf0.image",
],
"work_begin_cpu_id_exit": -1,
"boot_loader": [
- "/work/gem5/dist/binaries/boot_emm.arm"
+ "/dist/m5/system/binaries/boot_emm.arm"
],
"num_work_ids": 16
},
sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 948377 # Simulator instruction rate (inst/s)
-host_op_rate 1154497 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18491991143 # Simulator tick rate (ticks/s)
-host_mem_usage 582460 # Number of bytes of host memory used
-host_seconds 150.54 # Real time elapsed on the host
+host_inst_rate 800554 # Simulator instruction rate (inst/s)
+host_op_rate 974547 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15609662339 # Simulator tick rate (ticks/s)
+host_mem_usage 562564 # Number of bytes of host memory used
+host_seconds 178.34 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 11:24:30
-gem5 executing on e104799-lin, pid 30065
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:10
+gem5 executing on zizzer, pid 11544
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
sim_ticks 2802894699500 # Number of ticks simulated
final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 917511 # Simulator instruction rate (inst/s)
-host_op_rate 1117974 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17514936450 # Simulator tick rate (ticks/s)
-host_mem_usage 594132 # Number of bytes of host memory used
-host_seconds 160.03 # Real time elapsed on the host
+host_inst_rate 586939 # Simulator instruction rate (inst/s)
+host_op_rate 715176 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11204428729 # Simulator tick rate (ticks/s)
+host_mem_usage 574332 # Number of bytes of host memory used
+host_seconds 250.16 # Real time elapsed on the host
sim_insts 146828240 # Number of instructions simulated
sim_ops 178908039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 11:39:25
-gem5 executing on e104799-lin, pid 31608
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:33
+gem5 executing on zizzer, pid 11584
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 960961 # Simulator instruction rate (inst/s)
-host_op_rate 1169816 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18737357971 # Simulator tick rate (ticks/s)
-host_mem_usage 579868 # Number of bytes of host memory used
-host_seconds 148.57 # Real time elapsed on the host
+host_inst_rate 616731 # Simulator instruction rate (inst/s)
+host_op_rate 750771 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 12025369468 # Simulator tick rate (ticks/s)
+host_mem_usage 560084 # Number of bytes of host memory used
+host_seconds 231.50 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 13:19:17
-gem5 executing on e104799-lin, pid 9442
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:09
+gem5 executing on zizzer, pid 11535
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
sim_ticks 2871850306000 # Number of ticks simulated
final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 595194 # Simulator instruction rate (inst/s)
-host_op_rate 719909 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12993896386 # Simulator tick rate (ticks/s)
-host_mem_usage 612660 # Number of bytes of host memory used
-host_seconds 221.02 # Real time elapsed on the host
+host_inst_rate 357173 # Simulator instruction rate (inst/s)
+host_op_rate 432014 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7797571327 # Simulator tick rate (ticks/s)
+host_mem_usage 598232 # Number of bytes of host memory used
+host_seconds 368.30 # Real time elapsed on the host
sim_insts 131546959 # Number of instructions simulated
sim_ops 159110973 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 12:27:38
-gem5 executing on e104799-lin, pid 4347
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:09
+gem5 executing on zizzer, pid 11541
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
sim_ticks 2909596171500 # Number of ticks simulated
final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 612420 # Simulator instruction rate (inst/s)
-host_op_rate 738388 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15845377688 # Simulator tick rate (ticks/s)
-host_mem_usage 579872 # Number of bytes of host memory used
-host_seconds 183.62 # Real time elapsed on the host
+host_inst_rate 364808 # Simulator instruction rate (inst/s)
+host_op_rate 439844 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9438806072 # Simulator tick rate (ticks/s)
+host_mem_usage 560272 # Number of bytes of host memory used
+host_seconds 308.26 # Real time elapsed on the host
sim_insts 112455206 # Number of instructions simulated
sim_ops 135585876 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 11:36:43
-gem5 executing on e104799-lin, pid 31310
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:10
+gem5 executing on zizzer, pid 11555
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
Global frequency set at 1000000000000 ticks per second
sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 949157 # Simulator instruction rate (inst/s)
-host_op_rate 1155446 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18507193552 # Simulator tick rate (ticks/s)
-host_mem_usage 578592 # Number of bytes of host memory used
-host_seconds 150.42 # Real time elapsed on the host
+host_inst_rate 596623 # Simulator instruction rate (inst/s)
+host_op_rate 726292 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11633285247 # Simulator tick rate (ticks/s)
+host_mem_usage 560420 # Number of bytes of host memory used
+host_seconds 239.30 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 11:29:52
-gem5 executing on e104799-lin, pid 30613
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:22
+gem5 executing on zizzer, pid 11577
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 2909670971500 # Number of ticks simulated
final_tick 2909670971500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 618646 # Simulator instruction rate (inst/s)
-host_op_rate 745891 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16006919548 # Simulator tick rate (ticks/s)
-host_mem_usage 578852 # Number of bytes of host memory used
-host_seconds 181.78 # Real time elapsed on the host
+host_inst_rate 363443 # Simulator instruction rate (inst/s)
+host_op_rate 438198 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9403770867 # Simulator tick rate (ticks/s)
+host_mem_usage 560672 # Number of bytes of host memory used
+host_seconds 309.42 # Real time elapsed on the host
sim_insts 112454909 # Number of instructions simulated
sim_ops 135585028 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 15:10:31
-gem5 started Dec 4 2015 15:38:36
-gem5 executing on e104799-lin, pid 32389
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:47
+gem5 executing on zizzer, pid 10148
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5112152301500 because m5_exit instruction encountered
sim_ticks 5112152301500 # Number of ticks simulated
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 973581 # Simulator instruction rate (inst/s)
-host_op_rate 1993134 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24877176621 # Simulator tick rate (ticks/s)
-host_mem_usage 614804 # Number of bytes of host memory used
-host_seconds 205.50 # Real time elapsed on the host
+host_inst_rate 631335 # Simulator instruction rate (inst/s)
+host_op_rate 1292481 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16132023743 # Simulator tick rate (ticks/s)
+host_mem_usage 604612 # Number of bytes of host memory used
+host_seconds 316.89 # Real time elapsed on the host
sim_insts 200066731 # Number of instructions simulated
sim_ops 409580371 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/z/atgutier/gem5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 15:10:31
-gem5 started Dec 4 2015 15:10:45
-gem5 executing on e104799-lin, pid 29579
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:47
+gem5 executing on zizzer, pid 10143
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5194947216500 because m5_exit instruction encountered
sim_ticks 5194947216500 # Number of ticks simulated
final_tick 5194947216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 724563 # Simulator instruction rate (inst/s)
-host_op_rate 1396583 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29306793052 # Simulator tick rate (ticks/s)
-host_mem_usage 614800 # Number of bytes of host memory used
-host_seconds 177.26 # Real time elapsed on the host
+host_inst_rate 409072 # Simulator instruction rate (inst/s)
+host_op_rate 788480 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16545970820 # Simulator tick rate (ticks/s)
+host_mem_usage 604904 # Number of bytes of host memory used
+host_seconds 313.97 # Real time elapsed on the host
sim_insts 128436556 # Number of instructions simulated
sim_ops 247559476 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=drivesys.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/dist/m5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/configs/boot/netperf-server.rcS
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/atgutier/gem5/gem5/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
[drivesys.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[drivesys.disk2]
[drivesys.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[drivesys.dvfs_handler]
[drivesys.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[drivesys.terminal]
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=testsys.clk_domain
-console=/work/gem5/dist/binaries/console
+console=/dist/m5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-pal=/work/gem5/dist/binaries/ts_osfpal
-readfile=/work/gem5/outgoing/gem5_2/configs/boot/netperf-stream-client.rcS
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/atgutier/gem5/gem5/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
[testsys.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[testsys.disk2]
[testsys.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[testsys.dvfs_handler]
[testsys.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[testsys.terminal]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 10:28:58
-gem5 started Dec 4 2015 10:42:31
-gem5 executing on e104799-lin, pid 22915
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:29
+gem5 executing on zizzer, pid 26179
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /work/gem5/dist/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 4321620817500 because checkpoint
sim_ticks 200409271000 # Number of ticks simulated
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 12150896 # Simulator instruction rate (inst/s)
-host_op_rate 12150892 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4649177813 # Simulator tick rate (ticks/s)
-host_mem_usage 500080 # Number of bytes of host memory used
-host_seconds 43.11 # Real time elapsed on the host
+host_inst_rate 7045290 # Simulator instruction rate (inst/s)
+host_op_rate 7045287 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2695669073 # Simulator tick rate (ticks/s)
+host_mem_usage 476352 # Number of bytes of host memory used
+host_seconds 74.35 # Real time elapsed on the host
sim_insts 523780905 # Number of instructions simulated
sim_ops 523780905 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
sim_ticks 407341500 # Number of ticks simulated
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 5761027657 # Simulator instruction rate (inst/s)
-host_op_rate 5760057644 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4478236963 # Simulator tick rate (ticks/s)
-host_mem_usage 500080 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 3614433690 # Simulator instruction rate (inst/s)
+host_op_rate 3613747861 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2809493050 # Simulator tick rate (ticks/s)
+host_mem_usage 476352 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 523853183 # Number of instructions simulated
sim_ops 523853183 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:24
-gem5 executing on ribera.cs.wisc.edu, pid 29048
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:52
+gem5 executing on zizzer, pid 26256
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 37553000 # Number of ticks simulated
final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55108 # Simulator instruction rate (inst/s)
-host_op_rate 55099 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 323251479 # Simulator tick rate (ticks/s)
-host_mem_usage 290176 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 64031 # Simulator instruction rate (inst/s)
+host_op_rate 64014 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 375517232 # Simulator tick rate (ticks/s)
+host_mem_usage 231080 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:08
-gem5 executing on ribera.cs.wisc.edu, pid 29145
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26149
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 21900500 # Number of ticks simulated
final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59160 # Simulator instruction rate (inst/s)
-host_op_rate 59150 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 203265202 # Simulator tick rate (ticks/s)
-host_mem_usage 292228 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 48553 # Simulator instruction rate (inst/s)
+host_op_rate 48543 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 166810792 # Simulator tick rate (ticks/s)
+host_mem_usage 232316 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:47
-gem5 executing on ribera.cs.wisc.edu, pid 29075
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:28
+gem5 executing on zizzer, pid 26169
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1057772 # Simulator instruction rate (inst/s)
-host_op_rate 1055326 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 528762156 # Simulator tick rate (ticks/s)
-host_mem_usage 277832 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 110246 # Simulator instruction rate (inst/s)
+host_op_rate 110196 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55296654 # Simulator tick rate (ticks/s)
+host_mem_usage 220244 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 7583 # Transaction distribution
-system.membus.trans_dist::ReadResp 7583 # Transaction distribution
-system.membus.trans_dist::WriteReq 865 # Transaction distribution
-system.membus.trans_dist::WriteResp 865 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 8448 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram
-system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 8448 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
+system.membus.trans_dist::ReadReq 7583 # Transaction distribution
+system.membus.trans_dist::ReadResp 7583 # Transaction distribution
+system.membus.trans_dist::WriteReq 865 # Transaction distribution
+system.membus.trans_dist::WriteResp 865 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 8448 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram
+system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 8448 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:41:13
-gem5 started Nov 15 2015 14:41:38
-gem5 executing on ribera.cs.wisc.edu, pid 32149
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Dec 11 2015 20:05:44
+gem5 started Dec 11 2015 20:06:17
+gem5 executing on zizzer, pid 37024
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 121460 # Number of ticks simulated
final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 24898 # Simulator instruction rate (inst/s)
-host_op_rate 24896 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 473190 # Simulator tick rate (ticks/s)
-host_mem_usage 448380 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
+host_inst_rate 18505 # Simulator instruction rate (inst/s)
+host_op_rate 18504 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 351701 # Simulator tick rate (ticks/s)
+host_mem_usage 388732 # Number of bytes of host memory used
+host_seconds 0.35 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:46:21
-gem5 started Nov 15 2015 14:46:44
-gem5 executing on ribera.cs.wisc.edu, pid 1174
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Dec 11 2015 20:10:49
+gem5 started Dec 11 2015 20:11:27
+gem5 executing on zizzer, pid 42477
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 108694 # Number of ticks simulated
final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 34181 # Simulator instruction rate (inst/s)
-host_op_rate 34178 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 581310 # Simulator tick rate (ticks/s)
-host_mem_usage 451520 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 21195 # Simulator instruction rate (inst/s)
+host_op_rate 21193 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 360456 # Simulator tick rate (ticks/s)
+host_mem_usage 391840 # Number of bytes of host memory used
+host_seconds 0.30 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:51:28
-gem5 started Nov 15 2015 14:51:58
-gem5 executing on ribera.cs.wisc.edu, pid 2899
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Dec 11 2015 20:15:50
+gem5 started Dec 11 2015 20:16:20
+gem5 executing on zizzer, pid 47639
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 108253 # Number of ticks simulated
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 35277 # Simulator instruction rate (inst/s)
-host_op_rate 35272 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 597494 # Simulator tick rate (ticks/s)
-host_mem_usage 449432 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 16244 # Simulator instruction rate (inst/s)
+host_op_rate 16243 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 275161 # Simulator tick rate (ticks/s)
+host_mem_usage 389764 # Number of bytes of host memory used
+host_seconds 0.39 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:35:53
-gem5 started Nov 15 2015 14:36:15
-gem5 executing on ribera.cs.wisc.edu, pid 30620
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Dec 11 2015 20:00:36
+gem5 started Dec 11 2015 20:01:07
+gem5 executing on zizzer, pid 31719
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 86673 # Number of ticks simulated
final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 33775 # Simulator instruction rate (inst/s)
-host_op_rate 33772 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 458039 # Simulator tick rate (ticks/s)
-host_mem_usage 448324 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 24441 # Simulator instruction rate (inst/s)
+host_op_rate 24439 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 331452 # Simulator tick rate (ticks/s)
+host_mem_usage 389356 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:20
-gem5 executing on ribera.cs.wisc.edu, pid 29152
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:38
+gem5 executing on zizzer, pid 26203
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 107210 # Number of ticks simulated
final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 51155 # Simulator instruction rate (inst/s)
-host_op_rate 51148 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 858029 # Simulator tick rate (ticks/s)
-host_mem_usage 447104 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 30588 # Simulator instruction rate (inst/s)
+host_op_rate 30584 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 513061 # Simulator tick rate (ticks/s)
+host_mem_usage 388380 # Number of bytes of host memory used
+host_seconds 0.21 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:46
-gem5 executing on ribera.cs.wisc.edu, pid 29113
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:42
+gem5 executing on zizzer, pid 26242
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 35667500 # Number of ticks simulated
final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123464 # Simulator instruction rate (inst/s)
-host_op_rate 123421 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 688686311 # Simulator tick rate (ticks/s)
-host_mem_usage 290180 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 3576 # Simulator instruction rate (inst/s)
+host_op_rate 3576 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19962115 # Simulator tick rate (ticks/s)
+host_mem_usage 230248 # Number of bytes of host memory used
+host_seconds 1.79 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:19
-gem5 executing on ribera.cs.wisc.edu, pid 29096
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:29
+gem5 executing on zizzer, pid 26176
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 20075000 # Number of ticks simulated
final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 43924 # Simulator instruction rate (inst/s)
-host_op_rate 43910 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 340901575 # Simulator tick rate (ticks/s)
-host_mem_usage 289896 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 11823 # Simulator instruction rate (inst/s)
+host_op_rate 11822 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91797329 # Simulator tick rate (ticks/s)
+host_mem_usage 230008 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:33
-gem5 executing on ribera.cs.wisc.edu, pid 29168
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:41
+gem5 executing on zizzer, pid 26235
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 12363500 # Number of ticks simulated
final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 30943 # Simulator instruction rate (inst/s)
-host_op_rate 30935 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 160195252 # Simulator tick rate (ticks/s)
-host_mem_usage 290920 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 19595 # Simulator instruction rate (inst/s)
+host_op_rate 19590 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 101447809 # Simulator tick rate (ticks/s)
+host_mem_usage 231216 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:24
-gem5 executing on ribera.cs.wisc.edu, pid 29046
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:28
+gem5 executing on zizzer, pid 26173
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 828617 # Simulator instruction rate (inst/s)
-host_op_rate 824640 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 413479924 # Simulator tick rate (ticks/s)
-host_mem_usage 276508 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
+host_inst_rate 48732 # Simulator instruction rate (inst/s)
+host_op_rate 48711 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24515166 # Simulator tick rate (ticks/s)
+host_mem_usage 219316 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 3000 # Transaction distribution
-system.membus.trans_dist::ReadResp 3000 # Transaction distribution
-system.membus.trans_dist::WriteReq 294 # Transaction distribution
-system.membus.trans_dist::WriteResp 294 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3294 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram
-system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3294 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
+system.membus.trans_dist::ReadReq 3000 # Transaction distribution
+system.membus.trans_dist::ReadResp 3000 # Transaction distribution
+system.membus.trans_dist::WriteReq 294 # Transaction distribution
+system.membus.trans_dist::WriteResp 294 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3294 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram
+system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3294 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:41:13
-gem5 started Nov 15 2015 14:41:38
-gem5 executing on ribera.cs.wisc.edu, pid 32151
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Dec 11 2015 20:05:44
+gem5 started Dec 11 2015 20:06:17
+gem5 executing on zizzer, pid 37027
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 45733 # Number of ticks simulated
final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 14502 # Simulator instruction rate (inst/s)
-host_op_rate 14500 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 257305 # Simulator tick rate (ticks/s)
-host_mem_usage 447076 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 19080 # Simulator instruction rate (inst/s)
+host_op_rate 19075 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 338419 # Simulator tick rate (ticks/s)
+host_mem_usage 387604 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:46:21
-gem5 started Nov 15 2015 14:46:44
-gem5 executing on ribera.cs.wisc.edu, pid 1172
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Dec 11 2015 20:10:49
+gem5 started Dec 11 2015 20:11:27
+gem5 executing on zizzer, pid 42488
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 41712 # Number of ticks simulated
final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 17217 # Simulator instruction rate (inst/s)
-host_op_rate 17215 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 278615 # Simulator tick rate (ticks/s)
-host_mem_usage 449188 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 16080 # Simulator instruction rate (inst/s)
+host_op_rate 16077 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 260182 # Simulator tick rate (ticks/s)
+host_mem_usage 389928 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:51:28
-gem5 started Nov 15 2015 14:51:55
-gem5 executing on ribera.cs.wisc.edu, pid 2889
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Dec 11 2015 20:15:50
+gem5 started Dec 11 2015 20:16:20
+gem5 executing on zizzer, pid 47645
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 40527 # Number of ticks simulated
final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 24433 # Simulator instruction rate (inst/s)
-host_op_rate 24429 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 384119 # Simulator tick rate (ticks/s)
-host_mem_usage 448124 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 13852 # Simulator instruction rate (inst/s)
+host_op_rate 13850 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 217785 # Simulator tick rate (ticks/s)
+host_mem_usage 388588 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:35:53
-gem5 started Nov 15 2015 14:36:14
-gem5 executing on ribera.cs.wisc.edu, pid 30619
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+gem5 compiled Dec 11 2015 20:00:36
+gem5 started Dec 11 2015 20:01:07
+gem5 executing on zizzer, pid 31723
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 32936 # Number of ticks simulated
final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 24441 # Simulator instruction rate (inst/s)
-host_op_rate 24437 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 312277 # Simulator tick rate (ticks/s)
-host_mem_usage 448040 # Number of bytes of host memory used
+host_inst_rate 23563 # Simulator instruction rate (inst/s)
+host_op_rate 23558 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 301005 # Simulator tick rate (ticks/s)
+host_mem_usage 388376 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:22
-gem5 executing on ribera.cs.wisc.edu, pid 29157
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:40
+gem5 executing on zizzer, pid 26219
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 41659 # Number of ticks simulated
final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 33721 # Simulator instruction rate (inst/s)
-host_op_rate 33714 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 544888 # Simulator tick rate (ticks/s)
-host_mem_usage 445796 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 17997 # Simulator instruction rate (inst/s)
+host_op_rate 17994 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 290838 # Simulator tick rate (ticks/s)
+host_mem_usage 386736 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:57
-gem5 executing on ribera.cs.wisc.edu, pid 29136
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:50
+gem5 executing on zizzer, pid 26249
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 18239500 # Number of ticks simulated
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60500 # Simulator instruction rate (inst/s)
-host_op_rate 60473 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 427843204 # Simulator tick rate (ticks/s)
-host_mem_usage 288876 # Number of bytes of host memory used
+host_inst_rate 62631 # Simulator instruction rate (inst/s)
+host_op_rate 62591 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 442744438 # Simulator tick rate (ticks/s)
+host_mem_usage 229340 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:29:19
-gem5 executing on ribera.cs.wisc.edu, pid 11166
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:49:24
+gem5 executing on zizzer, pid 11619
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 29949500 # Number of ticks simulated
final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53802 # Simulator instruction rate (inst/s)
-host_op_rate 62972 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 349767389 # Simulator tick rate (ticks/s)
-host_mem_usage 307220 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 42320 # Simulator instruction rate (inst/s)
+host_op_rate 49532 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 275104580 # Simulator tick rate (ticks/s)
+host_mem_usage 247476 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 4605 # Number of instructions simulated
sim_ops 5391 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:29:13
-gem5 executing on ribera.cs.wisc.edu, pid 11155
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:49:26
+gem5 executing on zizzer, pid 11626
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 17170000 # Number of ticks simulated
final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 30630 # Simulator instruction rate (inst/s)
-host_op_rate 35868 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 114456188 # Simulator tick rate (ticks/s)
-host_mem_usage 308252 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 17652 # Simulator instruction rate (inst/s)
+host_op_rate 20671 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 65987169 # Simulator tick rate (ticks/s)
+host_mem_usage 248556 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:25:11
-gem5 executing on ribera.cs.wisc.edu, pid 11031
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:09
+gem5 executing on zizzer, pid 11532
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 18741000 # Number of ticks simulated
final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 9085 # Simulator instruction rate (inst/s)
-host_op_rate 10640 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37077299 # Simulator tick rate (ticks/s)
-host_mem_usage 304792 # Number of bytes of host memory used
-host_seconds 0.51 # Real time elapsed on the host
+host_inst_rate 24610 # Simulator instruction rate (inst/s)
+host_op_rate 28818 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100406204 # Simulator tick rate (ticks/s)
+host_mem_usage 244944 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:28:19
-gem5 executing on ribera.cs.wisc.edu, pid 11113
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:49:17
+gem5 executing on zizzer, pid 11612
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 30690 # Simulator instruction rate (inst/s)
-host_op_rate 35938 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18006429 # Simulator tick rate (ticks/s)
-host_mem_usage 296212 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 39910 # Simulator instruction rate (inst/s)
+host_op_rate 46729 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23410900 # Simulator tick rate (ticks/s)
+host_mem_usage 236816 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:29:18
-gem5 executing on ribera.cs.wisc.edu, pid 11161
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:10
+gem5 executing on zizzer, pid 11558
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95191 # Simulator instruction rate (inst/s)
-host_op_rate 111442 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55823840 # Simulator tick rate (ticks/s)
-host_mem_usage 296212 # Number of bytes of host memory used
+host_inst_rate 93235 # Simulator instruction rate (inst/s)
+host_op_rate 109134 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54661340 # Simulator tick rate (ticks/s)
+host_mem_usage 236444 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:28:09
-gem5 executing on ribera.cs.wisc.edu, pid 11108
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:49:28
+gem5 executing on zizzer, pid 11633
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 28298500 # Number of ticks simulated
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 102105 # Simulator instruction rate (inst/s)
-host_op_rate 119142 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 632323230 # Simulator tick rate (ticks/s)
-host_mem_usage 306200 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 71050 # Simulator instruction rate (inst/s)
+host_op_rate 82905 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 439999745 # Simulator tick rate (ticks/s)
+host_mem_usage 246456 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 4566 # Number of instructions simulated
sim_ops 5330 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:56:12
-gem5 started Nov 15 2015 14:56:33
-gem5 executing on ribera.cs.wisc.edu, pid 4270
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
+gem5 compiled Dec 11 2015 20:20:45
+gem5 started Dec 11 2015 20:21:19
+gem5 executing on zizzer, pid 52953
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 22454000 # Number of ticks simulated
final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46477 # Simulator instruction rate (inst/s)
-host_op_rate 46469 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 209234861 # Simulator tick rate (ticks/s)
-host_mem_usage 289428 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 32335 # Simulator instruction rate (inst/s)
+host_op_rate 32329 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 145565694 # Simulator tick rate (ticks/s)
+host_mem_usage 230124 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 4986 # Number of instructions simulated
sim_ops 4986 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:56:12
-gem5 started Nov 15 2015 14:56:34
-gem5 executing on ribera.cs.wisc.edu, pid 4273
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:20:45
+gem5 started Dec 11 2015 20:21:19
+gem5 executing on zizzer, pid 52939
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2812000 # Number of ticks simulated
final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 65844 # Simulator instruction rate (inst/s)
-host_op_rate 65830 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32908431 # Simulator tick rate (ticks/s)
-host_mem_usage 267356 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 121410 # Simulator instruction rate (inst/s)
+host_op_rate 121348 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60644587 # Simulator tick rate (ticks/s)
+host_mem_usage 218112 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 8001422475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2805832148 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10807254623 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 6757 # Transaction distribution
-system.membus.trans_dist::ReadResp 6757 # Transaction distribution
-system.membus.trans_dist::WriteReq 901 # Transaction distribution
-system.membus.trans_dist::WriteResp 901 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 7658 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram
-system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 7658 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
+system.membus.trans_dist::ReadReq 6757 # Transaction distribution
+system.membus.trans_dist::ReadResp 6757 # Transaction distribution
+system.membus.trans_dist::WriteReq 901 # Transaction distribution
+system.membus.trans_dist::WriteResp 901 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7658 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram
+system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 7658 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:56:12
-gem5 started Nov 15 2015 14:56:33
-gem5 executing on ribera.cs.wisc.edu, pid 4271
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
+gem5 compiled Dec 11 2015 20:20:45
+gem5 started Dec 11 2015 20:21:19
+gem5 executing on zizzer, pid 52942
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 100307 # Number of ticks simulated
final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 40822 # Simulator instruction rate (inst/s)
-host_op_rate 40816 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 727880 # Simulator tick rate (ticks/s)
-host_mem_usage 445332 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 21348 # Simulator instruction rate (inst/s)
+host_op_rate 21346 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 380685 # Simulator tick rate (ticks/s)
+host_mem_usage 386772 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:56:12
-gem5 started Nov 15 2015 14:56:35
-gem5 executing on ribera.cs.wisc.edu, pid 4274
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
+gem5 compiled Dec 11 2015 20:20:45
+gem5 started Dec 11 2015 20:21:19
+gem5 executing on zizzer, pid 52937
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 33912500 # Number of ticks simulated
final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 143778 # Simulator instruction rate (inst/s)
-host_op_rate 143707 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 866170043 # Simulator tick rate (ticks/s)
-host_mem_usage 287376 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 76753 # Simulator instruction rate (inst/s)
+host_op_rate 76732 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 462561711 # Simulator tick rate (ticks/s)
+host_mem_usage 228212 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
-Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:02:54
-gem5 started Nov 15 2015 15:03:14
-gem5 executing on ribera.cs.wisc.edu, pid 6374
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
+gem5 compiled Dec 11 2015 20:27:54
+gem5 started Dec 11 2015 20:28:28
+gem5 executing on zizzer, pid 60772
+command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 19923000 # Number of ticks simulated
final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49730 # Simulator instruction rate (inst/s)
-host_op_rate 49722 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 171002739 # Simulator tick rate (ticks/s)
-host_mem_usage 287488 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 39341 # Simulator instruction rate (inst/s)
+host_op_rate 39333 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 135269529 # Simulator tick rate (ticks/s)
+host_mem_usage 228324 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout
-Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:02:54
-gem5 started Nov 15 2015 15:03:14
-gem5 executing on ribera.cs.wisc.edu, pid 6373
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:27:54
+gem5 started Dec 11 2015 20:28:29
+gem5 executing on zizzer, pid 60780
+command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1326844 # Simulator instruction rate (inst/s)
-host_op_rate 1322603 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 659230594 # Simulator tick rate (ticks/s)
-host_mem_usage 274036 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
+host_inst_rate 100862 # Simulator instruction rate (inst/s)
+host_op_rate 100821 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50380396 # Simulator tick rate (ticks/s)
+host_mem_usage 216424 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 6754 # Transaction distribution
-system.membus.trans_dist::ReadResp 6754 # Transaction distribution
-system.membus.trans_dist::WriteReq 1046 # Transaction distribution
-system.membus.trans_dist::WriteResp 1046 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 7800 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram
-system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 7800 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5793 # Class of executed instruction
+system.membus.trans_dist::ReadReq 6754 # Transaction distribution
+system.membus.trans_dist::ReadResp 6754 # Transaction distribution
+system.membus.trans_dist::WriteReq 1046 # Transaction distribution
+system.membus.trans_dist::WriteResp 1046 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 7800 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram
+system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 7800 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:09
-gem5 executing on ribera.cs.wisc.edu, pid 7745
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:38
+gem5 executing on zizzer, pid 884
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 399685 # Simulator instruction rate (inst/s)
-host_op_rate 399265 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 201759641 # Simulator tick rate (ticks/s)
-host_mem_usage 276260 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 101577 # Simulator instruction rate (inst/s)
+host_op_rate 101519 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51322332 # Simulator tick rate (ticks/s)
+host_mem_usage 218804 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 6085 # Transaction distribution
-system.membus.trans_dist::ReadResp 6085 # Transaction distribution
-system.membus.trans_dist::WriteReq 673 # Transaction distribution
-system.membus.trans_dist::WriteResp 673 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 6758 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram
-system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 6758 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 5390 # number of cpu cycles simulated
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5370 # Class of executed instruction
+system.membus.trans_dist::ReadReq 6085 # Transaction distribution
+system.membus.trans_dist::ReadResp 6085 # Transaction distribution
+system.membus.trans_dist::WriteReq 673 # Transaction distribution
+system.membus.trans_dist::WriteResp 673 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 6758 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram
+system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 6758 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:11
-gem5 executing on ribera.cs.wisc.edu, pid 7749
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:38
+gem5 executing on zizzer, pid 878
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 81703 # Number of ticks simulated
final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 20108 # Simulator instruction rate (inst/s)
-host_op_rate 20107 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 308374 # Simulator tick rate (ticks/s)
-host_mem_usage 445712 # Number of bytes of host memory used
-host_seconds 0.27 # Real time elapsed on the host
+host_inst_rate 35925 # Simulator instruction rate (inst/s)
+host_op_rate 35919 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 550812 # Simulator tick rate (ticks/s)
+host_mem_usage 387260 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:47
-gem5 executing on ribera.cs.wisc.edu, pid 7821
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:39
+gem5 executing on zizzer, pid 890
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 30526500 # Number of ticks simulated
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113634 # Simulator instruction rate (inst/s)
-host_op_rate 113590 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 650686714 # Simulator tick rate (ticks/s)
-host_mem_usage 287764 # Number of bytes of host memory used
+host_inst_rate 114442 # Simulator instruction rate (inst/s)
+host_op_rate 114390 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 655215079 # Simulator tick rate (ticks/s)
+host_mem_usage 228624 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:38
-gem5 executing on ribera.cs.wisc.edu, pid 9899
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:48
+gem5 executing on zizzer, pid 10164
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 20818000 # Number of ticks simulated
final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 30520 # Simulator instruction rate (inst/s)
-host_op_rate 55287 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 118073605 # Simulator tick rate (ticks/s)
-host_mem_usage 307952 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 24719 # Simulator instruction rate (inst/s)
+host_op_rate 44779 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95631897 # Simulator tick rate (ticks/s)
+host_mem_usage 249240 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:25
-gem5 executing on ribera.cs.wisc.edu, pid 9884
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:46
+gem5 executing on zizzer, pid 10133
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64313 # Simulator instruction rate (inst/s)
-host_op_rate 116481 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 67080627 # Simulator tick rate (ticks/s)
-host_mem_usage 295912 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 91120 # Simulator instruction rate (inst/s)
+host_op_rate 165011 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95016732 # Simulator tick rate (ticks/s)
+host_mem_usage 236704 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:48
-gem5 executing on ribera.cs.wisc.edu, pid 9909
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:48
+gem5 executing on zizzer, pid 10157
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 87948 # Number of ticks simulated
final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 42645 # Simulator instruction rate (inst/s)
-host_op_rate 77244 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 696812 # Simulator tick rate (ticks/s)
-host_mem_usage 463856 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 29086 # Simulator instruction rate (inst/s)
+host_op_rate 52683 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 475254 # Simulator tick rate (ticks/s)
+host_mem_usage 405352 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:36
-gem5 executing on ribera.cs.wisc.edu, pid 9893
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:46
+gem5 executing on zizzer, pid 10136
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 30886500 # Number of ticks simulated
final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 96344 # Simulator instruction rate (inst/s)
-host_op_rate 174473 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 552644692 # Simulator tick rate (ticks/s)
-host_mem_usage 305908 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 73831 # Simulator instruction rate (inst/s)
+host_op_rate 133710 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 423540181 # Simulator tick rate (ticks/s)
+host_mem_usage 246764 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:33
-gem5 executing on ribera.cs.wisc.edu, pid 29163
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:40
+gem5 executing on zizzer, pid 26224
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 24832500 # Number of ticks simulated
final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44040 # Simulator instruction rate (inst/s)
-host_op_rate 44038 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 85804643 # Simulator tick rate (ticks/s)
-host_mem_usage 292816 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 35835 # Simulator instruction rate (inst/s)
+host_op_rate 35832 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69816273 # Simulator tick rate (ticks/s)
+host_mem_usage 233096 # Number of bytes of host memory used
+host_seconds 0.36 # Real time elapsed on the host
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:27
-gem5 executing on ribera.cs.wisc.edu, pid 7788
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:36
+gem5 executing on zizzer, pid 864
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 26944000 # Number of ticks simulated
final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 19173 # Simulator instruction rate (inst/s)
-host_op_rate 19172 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35783272 # Simulator tick rate (ticks/s)
-host_mem_usage 289736 # Number of bytes of host memory used
-host_seconds 0.75 # Real time elapsed on the host
+host_inst_rate 15232 # Simulator instruction rate (inst/s)
+host_op_rate 15231 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28427827 # Simulator tick rate (ticks/s)
+host_mem_usage 230656 # Number of bytes of host memory used
+host_seconds 0.95 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:23
-gem5 executing on ribera.cs.wisc.edu, pid 7778
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:37
+gem5 executing on zizzer, pid 870
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 893248 # Simulator instruction rate (inst/s)
-host_op_rate 892512 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 447738368 # Simulator tick rate (ticks/s)
-host_mem_usage 276192 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 19080 # Simulator instruction rate (inst/s)
+host_op_rate 19079 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9578180 # Simulator tick rate (ticks/s)
+host_mem_usage 218588 # Number of bytes of host memory used
+host_seconds 0.79 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 17432 # Transaction distribution
-system.membus.trans_dist::ReadResp 17432 # Transaction distribution
-system.membus.trans_dist::WriteReq 1442 # Transaction distribution
-system.membus.trans_dist::WriteResp 1442 # Transaction distribution
-system.membus.trans_dist::SwapReq 6 # Transaction distribution
-system.membus.trans_dist::SwapResp 6 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 18880 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram
-system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 18880 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15225 # number of cpu cycles simulated
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
+system.membus.trans_dist::ReadReq 17432 # Transaction distribution
+system.membus.trans_dist::ReadResp 17432 # Transaction distribution
+system.membus.trans_dist::WriteReq 1442 # Transaction distribution
+system.membus.trans_dist::WriteResp 1442 # Transaction distribution
+system.membus.trans_dist::SwapReq 6 # Transaction distribution
+system.membus.trans_dist::SwapResp 6 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 18880 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram
+system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 18880 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:11
-gem5 executing on ribera.cs.wisc.edu, pid 7750
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:36
+gem5 executing on zizzer, pid 856
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 44282500 # Number of ticks simulated
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 18923 # Simulator instruction rate (inst/s)
-host_op_rate 18923 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55265287 # Simulator tick rate (ticks/s)
-host_mem_usage 287684 # Number of bytes of host memory used
-host_seconds 0.80 # Real time elapsed on the host
+host_inst_rate 17131 # Simulator instruction rate (inst/s)
+host_op_rate 17131 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50030483 # Simulator tick rate (ticks/s)
+host_mem_usage 228520 # Number of bytes of host memory used
+host_seconds 0.89 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:36
-gem5 executing on ribera.cs.wisc.edu, pid 29061
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26140
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 405501000 # Number of ticks simulated
final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75076 # Simulator instruction rate (inst/s)
-host_op_rate 75060 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4725264699 # Simulator tick rate (ticks/s)
-host_mem_usage 672256 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 93588 # Simulator instruction rate (inst/s)
+host_op_rate 93555 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5888544376 # Simulator tick rate (ticks/s)
+host_mem_usage 613408 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6440 # Number of instructions simulated
sim_ops 6440 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:24
-gem5 executing on ribera.cs.wisc.edu, pid 29047
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:31
+gem5 executing on zizzer, pid 26193
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 61610000 # Number of ticks simulated
final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49684 # Simulator instruction rate (inst/s)
-host_op_rate 49677 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 475179877 # Simulator tick rate (ticks/s)
-host_mem_usage 677504 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 114193 # Simulator instruction rate (inst/s)
+host_op_rate 114151 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1091680385 # Simulator tick rate (ticks/s)
+host_mem_usage 617796 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 6440 # Number of instructions simulated
sim_ops 6440 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:28:21
-gem5 executing on ribera.cs.wisc.edu, pid 11118
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:21
+gem5 executing on zizzer, pid 11570
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 325849000 # Number of ticks simulated
final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72040 # Simulator instruction rate (inst/s)
-host_op_rate 83312 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4703708270 # Simulator tick rate (ticks/s)
-host_mem_usage 689424 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 62964 # Simulator instruction rate (inst/s)
+host_op_rate 72811 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4110489437 # Simulator tick rate (ticks/s)
+host_mem_usage 629232 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 4988 # Number of instructions simulated
sim_ops 5770 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:29:08
-gem5 executing on ribera.cs.wisc.edu, pid 11149
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:49:14
+gem5 executing on zizzer, pid 11605
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 49855000 # Number of ticks simulated
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95959 # Simulator instruction rate (inst/s)
-host_op_rate 110965 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 958463106 # Simulator tick rate (ticks/s)
-host_mem_usage 693524 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 90039 # Simulator instruction rate (inst/s)
+host_op_rate 104098 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 898984961 # Simulator tick rate (ticks/s)
+host_mem_usage 633916 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 4988 # Number of instructions simulated
sim_ops 5770 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:56:12
-gem5 started Nov 15 2015 14:56:35
-gem5 executing on ribera.cs.wisc.edu, pid 4275
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /scratch/nilay/GEM5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
+gem5 compiled Dec 11 2015 20:20:45
+gem5 started Dec 11 2015 20:21:19
+gem5 executing on zizzer, pid 52945
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 367783000 # Number of ticks simulated
final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59583 # Simulator instruction rate (inst/s)
-host_op_rate 59571 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3894944488 # Simulator tick rate (ticks/s)
-host_mem_usage 670484 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 74447 # Simulator instruction rate (inst/s)
+host_op_rate 74421 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4865103995 # Simulator tick rate (ticks/s)
+host_mem_usage 611372 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:56:12
-gem5 started Nov 15 2015 14:56:33
-gem5 executing on ribera.cs.wisc.edu, pid 4272
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /scratch/nilay/GEM5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
+gem5 compiled Dec 11 2015 20:20:45
+gem5 started Dec 11 2015 20:21:18
+gem5 executing on zizzer, pid 52934
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 58892000 # Number of ticks simulated
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114712 # Simulator instruction rate (inst/s)
-host_op_rate 114668 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1200321738 # Simulator tick rate (ticks/s)
-host_mem_usage 675732 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 100643 # Simulator instruction rate (inst/s)
+host_op_rate 100605 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1053107711 # Simulator tick rate (ticks/s)
+host_mem_usage 615936 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:36
-gem5 executing on ribera.cs.wisc.edu, pid 7807
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:38
+gem5 executing on zizzer, pid 888
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 333033000 # Number of ticks simulated
final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87961 # Simulator instruction rate (inst/s)
-host_op_rate 87937 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5277232874 # Simulator tick rate (ticks/s)
-host_mem_usage 670864 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 60032 # Simulator instruction rate (inst/s)
+host_op_rate 60015 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3601550992 # Simulator tick rate (ticks/s)
+host_mem_usage 611780 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5548 # Number of instructions simulated
sim_ops 5548 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:10
-gem5 executing on ribera.cs.wisc.edu, pid 7746
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:37
+gem5 executing on zizzer, pid 867
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 53334000 # Number of ticks simulated
final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107436 # Simulator instruction rate (inst/s)
-host_op_rate 107401 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1032139873 # Simulator tick rate (ticks/s)
-host_mem_usage 676112 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 25419 # Simulator instruction rate (inst/s)
+host_op_rate 25415 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 244292688 # Simulator tick rate (ticks/s)
+host_mem_usage 616436 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 5548 # Number of instructions simulated
sim_ops 5548 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:25
-gem5 executing on ribera.cs.wisc.edu, pid 9885
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:48
+gem5 executing on zizzer, pid 10154
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 445082000 # Number of ticks simulated
final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74510 # Simulator instruction rate (inst/s)
-host_op_rate 134510 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5803230709 # Simulator tick rate (ticks/s)
-host_mem_usage 689132 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 54663 # Simulator instruction rate (inst/s)
+host_op_rate 98678 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4257260134 # Simulator tick rate (ticks/s)
+host_mem_usage 629764 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5712 # Number of instructions simulated
sim_ops 10314 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:37
-gem5 executing on ribera.cs.wisc.edu, pid 9898
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:47
+gem5 executing on zizzer, pid 10146
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 55844000 # Number of ticks simulated
final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94366 # Simulator instruction rate (inst/s)
-host_op_rate 170344 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 922046609 # Simulator tick rate (ticks/s)
-host_mem_usage 693228 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 73824 # Simulator instruction rate (inst/s)
+host_op_rate 133267 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 721372990 # Simulator tick rate (ticks/s)
+host_mem_usage 634496 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5712 # Number of instructions simulated
sim_ops 10314 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
-Redirecting stdout to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:28:32
-gem5 executing on ribera.cs.wisc.edu, pid 11134
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:36
+gem5 executing on zizzer, pid 11591
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1253669 # Simulator instruction rate (inst/s)
-host_op_rate 1259913 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 749150887 # Simulator tick rate (ticks/s)
-host_mem_usage 433332 # Number of bytes of host memory used
-host_seconds 72.27 # Real time elapsed on the host
+host_inst_rate 678405 # Simulator instruction rate (inst/s)
+host_op_rate 681784 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 405392222 # Simulator tick rate (ticks/s)
+host_mem_usage 371440 # Number of bytes of host memory used
+host_seconds 133.55 # Real time elapsed on the host
sim_insts 90602408 # Number of instructions simulated
sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
-Redirecting stdout to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:28:05
-gem5 executing on ribera.cs.wisc.edu, pid 11103
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:48:13
+gem5 executing on zizzer, pid 11598
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 147148719500 # Number of ticks simulated
final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 682988 # Simulator instruction rate (inst/s)
-host_op_rate 686382 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1109563613 # Simulator tick rate (ticks/s)
-host_mem_usage 443324 # Number of bytes of host memory used
-host_seconds 132.62 # Real time elapsed on the host
+host_inst_rate 449018 # Simulator instruction rate (inst/s)
+host_op_rate 451250 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 729462903 # Simulator tick rate (ticks/s)
+host_mem_usage 381564 # Number of bytes of host memory used
+host_seconds 201.72 # Real time elapsed on the host
sim_insts 90576862 # Number of instructions simulated
sim_ops 91026991 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
-Redirecting stdout to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:39
-gem5 executing on ribera.cs.wisc.edu, pid 7812
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:36
+gem5 executing on zizzer, pid 860
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2069444 # Simulator instruction rate (inst/s)
-host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1037295392 # Simulator tick rate (ticks/s)
-host_mem_usage 412436 # Number of bytes of host memory used
-host_seconds 117.82 # Real time elapsed on the host
+host_inst_rate 1196156 # Simulator instruction rate (inst/s)
+host_op_rate 1196205 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 599565352 # Simulator tick rate (ticks/s)
+host_mem_usage 352760 # Number of bytes of host memory used
+host_seconds 203.84 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
-system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
-system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
-system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
-system.membus.trans_dist::SwapReq 3886 # Transaction distribution
-system.membus.trans_dist::SwapResp 3886 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
-system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 349547768 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431648 # number of cpu cycles simulated
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
+system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
+system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
+system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
+system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
+system.membus.trans_dist::SwapReq 3886 # Transaction distribution
+system.membus.trans_dist::SwapResp 3886 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
+system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 349547768 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
-Redirecting stdout to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:27
-gem5 executing on ribera.cs.wisc.edu, pid 9887
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:47
+gem5 executing on zizzer, pid 10140
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 883218 # Simulator instruction rate (inst/s)
-host_op_rate 1555205 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 944496615 # Simulator tick rate (ticks/s)
-host_mem_usage 440276 # Number of bytes of host memory used
-host_seconds 178.88 # Real time elapsed on the host
+host_inst_rate 621138 # Simulator instruction rate (inst/s)
+host_op_rate 1093725 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 664233757 # Simulator tick rate (ticks/s)
+host_mem_usage 379176 # Number of bytes of host memory used
+host_seconds 254.35 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:36
-gem5 executing on ribera.cs.wisc.edu, pid 29067
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:29
+gem5 executing on zizzer, pid 26187
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Skipping test: Test requires the 'EioProcess' SimObject.
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1967280 # Simulator instruction rate (inst/s)
-host_op_rate 1967137 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 983561172 # Simulator tick rate (ticks/s)
-host_mem_usage 278544 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
-sim_insts 500001 # Number of instructions simulated
-sim_ops 500001 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
-system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory
-system.physmem.bytes_written::total 417562 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 124435 # DTB read hits
-system.cpu.dtb.read_misses 8 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 124443 # DTB read accesses
-system.cpu.dtb.write_hits 56340 # DTB write hits
-system.cpu.dtb.write_misses 10 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 56350 # DTB write accesses
-system.cpu.dtb.data_hits 180775 # DTB hits
-system.cpu.dtb.data_misses 18 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 180793 # DTB accesses
-system.cpu.itb.fetch_hits 500019 # ITB hits
-system.cpu.itb.fetch_misses 13 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 500032 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 500032 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 500001 # Number of instructions committed
-system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu.num_func_calls 14357 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu.num_int_insts 474689 # number of integer instructions
-system.cpu.num_fp_insts 32 # number of float instructions
-system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 180793 # number of memory refs
-system.cpu.num_load_insts 124443 # Number of load instructions
-system.cpu.num_store_insts 56350 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 500032 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 59023 # Number of branches fetched
-system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 500019 # Class of executed instruction
-system.membus.trans_dist::ReadReq 624454 # Transaction distribution
-system.membus.trans_dist::ReadResp 624454 # Transaction distribution
-system.membus.trans_dist::WriteReq 56340 # Transaction distribution
-system.membus.trans_dist::WriteResp 56340 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 680794 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
-system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 680794 # Request fanout histogram
-
----------- End Simulation Statistics ----------
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:32
-gem5 executing on ribera.cs.wisc.edu, pid 29162
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26151
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Skipping test: Test requires the 'EioProcess' SimObject.
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000733 # Number of seconds simulated
-sim_ticks 733071500 # Number of ticks simulated
-final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1060991 # Simulator instruction rate (inst/s)
-host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1555451807 # Simulator tick rate (ticks/s)
-host_mem_usage 288660 # Number of bytes of host memory used
-host_seconds 0.47 # Real time elapsed on the host
-sim_insts 500001 # Number of instructions simulated
-sim_ops 500001 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 35183471 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39635970 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 74819441 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 35183471 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 35183471 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 124435 # DTB read hits
-system.cpu.dtb.read_misses 8 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 124443 # DTB read accesses
-system.cpu.dtb.write_hits 56340 # DTB write hits
-system.cpu.dtb.write_misses 10 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 56350 # DTB write accesses
-system.cpu.dtb.data_hits 180775 # DTB hits
-system.cpu.dtb.data_misses 18 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 180793 # DTB accesses
-system.cpu.itb.fetch_hits 500020 # ITB hits
-system.cpu.itb.fetch_misses 13 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 500033 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 1466143 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 500001 # Number of instructions committed
-system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu.num_func_calls 14357 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu.num_int_insts 474689 # number of integer instructions
-system.cpu.num_fp_insts 32 # number of float instructions
-system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 180793 # number of memory refs
-system.cpu.num_load_insts 124443 # Number of load instructions
-system.cpu.num_store_insts 56350 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1466143 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 59023 # Number of branches fetched
-system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 500019 # Class of executed instruction
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 286.668758 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.069987 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.069987 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
-system.cpu.dcache.overall_hits::total 180321 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
-system.cpu.dcache.overall_misses::total 454 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 19530000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 19530000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8618000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8618000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 28148000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 28148000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 28148000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 28148000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19215000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 19215000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8479000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8479000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27694000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 27694000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27694000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 27694000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 264.585152 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.129192 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.129192 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits
-system.cpu.icache.overall_hits::total 499617 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
-system.cpu.icache.overall_misses::total 403 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 24986500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 24986500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 24986500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 24986500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 24986500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 24986500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62001.240695 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62001.240695 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62001.240695 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62001.240695 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24583500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 24583500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24583500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 24583500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24583500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 24583500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61001.240695 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61001.240695 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 264.590924 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 216.089673 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008075 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.006595 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.014669 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 718 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 403 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 315 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 315 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
-system.cpu.l2cache.overall_misses::total 857 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 8270500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23979000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 23979000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18742500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 18742500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 23979000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 27013000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 50992000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 23979000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 27013000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 50992000 # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 403 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 403 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 315 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.240695 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.240695 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59500.583431 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59500.583431 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 403 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 315 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 315 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6880500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6880500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19949000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19949000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15592500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15592500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19949000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22473000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 42422000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19949000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22473000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 42422000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 857 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 718 # Transaction distribution
-system.membus.trans_dist::ReadExReq 139 # Transaction distribution
-system.membus.trans_dist::ReadExResp 139 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 857 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 857 # Request fanout histogram
-system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4285000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:26
-gem5 executing on ribera.cs.wisc.edu, pid 29051
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:30
+gem5 executing on zizzer, pid 26190
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Skipping test: Test requires the 'EioProcess' SimObject.
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1830318 # Simulator instruction rate (inst/s)
-host_op_rate 1830286 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 228795713 # Simulator tick rate (ticks/s)
-host_mem_usage 302752 # Number of bytes of host memory used
-host_seconds 1.09 # Real time elapsed on the host
-sim_insts 2000004 # Number of instructions simulated
-sim_ops 2000004 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.itb.fetch_hits 500019 # ITB hits
-system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.fetch_acv 0 # ITB acv
-system.cpu0.itb.fetch_accesses 500032 # ITB accesses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 500032 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 500001 # Number of instructions committed
-system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu0.num_func_calls 14357 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 474689 # number of integer instructions
-system.cpu0.num_fp_insts 32 # number of float instructions
-system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu0.num_mem_refs 180793 # number of memory refs
-system.cpu0.num_load_insts 124443 # Number of load instructions
-system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 500032 # Number of busy cycles
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.Branches 59023 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
-system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
-system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu0.dcache.writebacks::total 29 # number of writebacks
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
-system.cpu0.icache.overall_hits::total 499556 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu0.icache.writebacks::total 152 # number of writebacks
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.write_hits 56340 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_accesses 56350 # DTB write accesses
-system.cpu1.dtb.data_hits 180775 # DTB hits
-system.cpu1.dtb.data_misses 18 # DTB misses
-system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_accesses 180793 # DTB accesses
-system.cpu1.itb.fetch_hits 500019 # ITB hits
-system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500032 # ITB accesses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.numCycles 500032 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 500001 # Number of instructions committed
-system.cpu1.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474689 # number of integer instructions
-system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu1.num_mem_refs 180793 # number of memory refs
-system.cpu1.num_load_insts 124443 # Number of load instructions
-system.cpu1.num_store_insts 56350 # Number of store instructions
-system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 500032 # Number of busy cycles
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.Branches 59023 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 500019 # Class of executed instruction
-system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 180312 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 180312 # number of overall hits
-system.cpu1.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
-system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 180775 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu1.dcache.writebacks::total 29 # number of writebacks
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits
-system.cpu1.icache.overall_hits::total 499556 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
-system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu1.icache.writebacks::total 152 # number of writebacks
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dtb.fetch_hits 0 # ITB hits
-system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.fetch_acv 0 # ITB acv
-system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124435 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.write_hits 56340 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_accesses 56350 # DTB write accesses
-system.cpu2.dtb.data_hits 180775 # DTB hits
-system.cpu2.dtb.data_misses 18 # DTB misses
-system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180793 # DTB accesses
-system.cpu2.itb.fetch_hits 500019 # ITB hits
-system.cpu2.itb.fetch_misses 13 # ITB misses
-system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500032 # ITB accesses
-system.cpu2.itb.read_hits 0 # DTB read hits
-system.cpu2.itb.read_misses 0 # DTB read misses
-system.cpu2.itb.read_acv 0 # DTB read access violations
-system.cpu2.itb.read_accesses 0 # DTB read accesses
-system.cpu2.itb.write_hits 0 # DTB write hits
-system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.write_acv 0 # DTB write access violations
-system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.data_hits 0 # DTB hits
-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.data_acv 0 # DTB access violations
-system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.numCycles 500032 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 500001 # Number of instructions committed
-system.cpu2.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu2.num_func_calls 14357 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474689 # number of integer instructions
-system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180793 # number of memory refs
-system.cpu2.num_load_insts 124443 # Number of load instructions
-system.cpu2.num_store_insts 56350 # Number of store instructions
-system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 500032 # Number of busy cycles
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.Branches 59023 # Number of branches fetched
-system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 500019 # Class of executed instruction
-system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 180312 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 180312 # number of overall hits
-system.cpu2.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
-system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 180775 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes 0 # number of fast writes performed
-system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu2.dcache.writebacks::total 29 # number of writebacks
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits
-system.cpu2.icache.overall_hits::total 499556 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
-system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu2.icache.writebacks::total 152 # number of writebacks
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dtb.fetch_hits 0 # ITB hits
-system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.fetch_acv 0 # ITB acv
-system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.read_hits 124435 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_accesses 124443 # DTB read accesses
-system.cpu3.dtb.write_hits 56340 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_accesses 56350 # DTB write accesses
-system.cpu3.dtb.data_hits 180775 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
-system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_accesses 180793 # DTB accesses
-system.cpu3.itb.fetch_hits 500019 # ITB hits
-system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500032 # ITB accesses
-system.cpu3.itb.read_hits 0 # DTB read hits
-system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.read_acv 0 # DTB read access violations
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.write_hits 0 # DTB write hits
-system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.write_acv 0 # DTB write access violations
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.numCycles 500032 # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 500001 # Number of instructions committed
-system.cpu3.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474689 # number of integer instructions
-system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180793 # number of memory refs
-system.cpu3.num_load_insts 124443 # Number of load instructions
-system.cpu3.num_store_insts 56350 # Number of store instructions
-system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 500032 # Number of busy cycles
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.Branches 59023 # Number of branches fetched
-system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 500019 # Class of executed instruction
-system.cpu3.dcache.tags.replacements 61 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 180312 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 180312 # number of overall hits
-system.cpu3.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
-system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 180775 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu3.dcache.writebacks::total 29 # number of writebacks
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits
-system.cpu3.icache.overall_hits::total 499556 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
-system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu3.icache.writebacks::total 152 # number of writebacks
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
-system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 39936 # Number of tag accesses
-system.l2c.tags.data_accesses 39936 # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu0.data 454 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu1.data 454 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu2.data 454 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu3.data 454 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks 116 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 116 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks 608 # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total 608 # number of WritebackClean accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3428 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3428 # Request fanout histogram
-system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4556 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram
-
----------- End Simulation Statistics ----------
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:30:20
-gem5 executing on ribera.cs.wisc.edu, pid 29151
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26145
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Skipping test: Test requires the 'EioProcess' SimObject.
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000734 # Number of seconds simulated
-sim_ticks 733914500 # Number of ticks simulated
-final_tick 733914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 992162 # Simulator instruction rate (inst/s)
-host_op_rate 992153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 364079839 # Simulator tick rate (ticks/s)
-host_mem_usage 302744 # Number of bytes of host memory used
-host_seconds 2.02 # Real time elapsed on the host
-sim_insts 1999973 # Number of instructions simulated
-sim_ops 1999973 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35143058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39590443 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35143058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39590443 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35143058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39590443 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35143058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39590443 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 298934004 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35143058 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 140572233 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39590443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39590443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39590443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35143058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39590443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 298934004 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.itb.fetch_hits 500020 # ITB hits
-system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.fetch_acv 0 # ITB acv
-system.cpu0.itb.fetch_accesses 500033 # ITB accesses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1467829 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 500001 # Number of instructions committed
-system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu0.num_func_calls 14357 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 474689 # number of integer instructions
-system.cpu0.num_fp_insts 32 # number of float instructions
-system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu0.num_mem_refs 180793 # number of memory refs
-system.cpu0.num_load_insts 124443 # Number of load instructions
-system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1467829 # Number of busy cycles
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.Branches 59023 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 273.068294 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.068294 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.533337 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.533337 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
-system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
-system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19649000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8621000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 28270000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 28270000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 60645.061728 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62021.582734 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu0.dcache.writebacks::total 29 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19325000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8482000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27807000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27807000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 59645.061728 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 61021.582734 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 216.116668 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.116668 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422103 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.422103 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
-system.cpu0.icache.overall_hits::total 499557 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25776500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 25776500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 25776500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 25776500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 25776500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 25776500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 55672.786177 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 55672.786177 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 55672.786177 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 55672.786177 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu0.icache.writebacks::total 152 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 25313500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 25313500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 25313500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 25313500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 25313500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 25313500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 54672.786177 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.write_hits 56339 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_accesses 56349 # DTB write accesses
-system.cpu1.dtb.data_hits 180774 # DTB hits
-system.cpu1.dtb.data_misses 18 # DTB misses
-system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_accesses 180792 # DTB accesses
-system.cpu1.itb.fetch_hits 500014 # ITB hits
-system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500027 # ITB accesses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.numCycles 1467829 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 499995 # Number of instructions committed
-system.cpu1.committedOps 499995 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474683 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474683 # number of integer instructions
-system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654276 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371538 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu1.num_mem_refs 180792 # number of memory refs
-system.cpu1.num_load_insts 124443 # Number of load instructions
-system.cpu1.num_store_insts 56349 # Number of store instructions
-system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 1467829 # Number of busy cycles
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.Branches 59022 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu 300383 60.08% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 500013 # Class of executed instruction
-system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 273.065457 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.065457 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.533331 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.533331 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits
-system.cpu1.dcache.overall_hits::total 180311 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
-system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 19649000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8621500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 8621500 # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 28270500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 28270500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 60645.061728 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 62025.179856 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 62025.179856 # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu1.dcache.writebacks::total 29 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 19325000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 8482500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 8482500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 27807500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 27807500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 27807500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 59645.061728 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61025.179856 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 61025.179856 # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 216.114546 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.943844 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.114546 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422099 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.422099 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 499551 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 499551 # number of overall hits
-system.cpu1.icache.overall_hits::total 499551 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
-system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 25783000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 25783000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 25783000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 25783000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 25783000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 25783000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 500014 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 500014 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 500014 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 500014 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 500014 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 500014 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 55686.825054 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 55686.825054 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 55686.825054 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 55686.825054 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 55686.825054 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 55686.825054 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu1.icache.writebacks::total 152 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 25320000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 25320000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 25320000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 25320000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 25320000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 25320000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 54686.825054 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dtb.fetch_hits 0 # ITB hits
-system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.fetch_acv 0 # ITB acv
-system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124435 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.write_hits 56339 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_accesses 56349 # DTB write accesses
-system.cpu2.dtb.data_hits 180774 # DTB hits
-system.cpu2.dtb.data_misses 18 # DTB misses
-system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180792 # DTB accesses
-system.cpu2.itb.fetch_hits 500009 # ITB hits
-system.cpu2.itb.fetch_misses 13 # ITB misses
-system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500022 # ITB accesses
-system.cpu2.itb.read_hits 0 # DTB read hits
-system.cpu2.itb.read_misses 0 # DTB read misses
-system.cpu2.itb.read_acv 0 # DTB read access violations
-system.cpu2.itb.read_accesses 0 # DTB read accesses
-system.cpu2.itb.write_hits 0 # DTB write hits
-system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.write_acv 0 # DTB write access violations
-system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.data_hits 0 # DTB hits
-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.data_acv 0 # DTB access violations
-system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.numCycles 1467829 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 499990 # Number of instructions committed
-system.cpu2.committedOps 499990 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474678 # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu2.num_func_calls 14357 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474678 # number of integer instructions
-system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654270 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371533 # number of times the integer registers were written
-system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180791 # number of memory refs
-system.cpu2.num_load_insts 124442 # Number of load instructions
-system.cpu2.num_store_insts 56349 # Number of store instructions
-system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 1467829 # Number of busy cycles
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.Branches 59022 # Number of branches fetched
-system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu 300379 60.07% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124442 24.89% 88.73% # Class of executed instruction
-system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 500008 # Class of executed instruction
-system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 273.062707 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.062707 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.533326 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.533326 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 180311 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 180311 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 180311 # number of overall hits
-system.cpu2.dcache.overall_hits::total 180311 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
-system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 19649000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 8621000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 28270000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 28270000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 180774 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 180774 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 60645.061728 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 62021.582734 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes 0 # number of fast writes performed
-system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu2.dcache.writebacks::total 29 # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 19325000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 8482000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 27807000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 27807000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 59645.061728 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 61021.582734 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 216.112416 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.933045 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.112416 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422095 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.422095 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499546 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499546 # number of overall hits
-system.cpu2.icache.overall_hits::total 499546 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
-system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 25788500 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 25788500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 25788500 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 25788500 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 25788500 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 25788500 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500009 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500009 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500009 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500009 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500009 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500009 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 55698.704104 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 55698.704104 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 55698.704104 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 55698.704104 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 55698.704104 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 55698.704104 # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu2.icache.writebacks::total 152 # number of writebacks
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 25325500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 25325500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 25325500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 25325500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 25325500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 25325500 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 54698.704104 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dtb.fetch_hits 0 # ITB hits
-system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.fetch_acv 0 # ITB acv
-system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.read_hits 124433 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_accesses 124441 # DTB read accesses
-system.cpu3.dtb.write_hits 56339 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.data_hits 180772 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
-system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_accesses 180790 # DTB accesses
-system.cpu3.itb.fetch_hits 500006 # ITB hits
-system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500019 # ITB accesses
-system.cpu3.itb.read_hits 0 # DTB read hits
-system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.read_acv 0 # DTB read access violations
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.write_hits 0 # DTB write hits
-system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.write_acv 0 # DTB write access violations
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.numCycles 1467829 # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499987 # Number of instructions committed
-system.cpu3.committedOps 499987 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474675 # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474675 # number of integer instructions
-system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654265 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371530 # number of times the integer registers were written
-system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180790 # number of memory refs
-system.cpu3.num_load_insts 124441 # Number of load instructions
-system.cpu3.num_store_insts 56349 # Number of store instructions
-system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 1467829 # Number of busy cycles
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.Branches 59022 # Number of branches fetched
-system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300377 60.07% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 500005 # Class of executed instruction
-system.cpu3.dcache.tags.replacements 61 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 273.059955 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.059955 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.533320 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.533320 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 180309 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 180309 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 180309 # number of overall hits
-system.cpu3.dcache.overall_hits::total 180309 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
-system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 19649500 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 19649500 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 8621000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 28270500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 28270500 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 180772 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 180772 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 60646.604938 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 60646.604938 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 62021.582734 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu3.dcache.writebacks::total 29 # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 139 # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 19325500 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 19325500 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 8482000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 27807500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 27807500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 27807500 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 59646.604938 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 59646.604938 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 61021.582734 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 60059.395248 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 60059.395248 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 216.110261 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.926566 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.110261 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422090 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.422090 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500469 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500469 # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499543 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499543 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499543 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499543 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499543 # number of overall hits
-system.cpu3.icache.overall_hits::total 499543 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
-system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 25793000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 25793000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 25793000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 25793000 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 25793000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 25793000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 500006 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 500006 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 500006 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 500006 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 500006 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 500006 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 55708.423326 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 55708.423326 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 55708.423326 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 55708.423326 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 55708.423326 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 55708.423326 # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu3.icache.writebacks::total 152 # number of writebacks
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 25330000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 25330000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 25330000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 25330000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 25330000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 25330000 # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 54708.423326 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1940.317854 # Cycle average of tags in use
-system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.170012 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 264.661885 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 216.132475 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 264.659128 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 216.130297 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 264.656363 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 216.128138 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 264.653570 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 216.125986 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000262 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004038 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003298 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004038 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003298 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004038 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003298 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004038 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003298 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029607 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 39936 # Number of tag accesses
-system.l2c.tags.data_accesses 39936 # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu0.data 454 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu1.data 454 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu2.data 454 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu3.data 454 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data 8272000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 8272500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 8272000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 8272500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 33089000 # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst 23984000 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst 23989500 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst 23995500 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst 24001000 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total 95970000 # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data 18743500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 18743500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data 18743500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data 18744000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 74974500 # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 23984000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 27015500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 23989500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 27016000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 23995500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 27015500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 24001000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 27016500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 204033500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 23984000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 27015500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 23989500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 27016000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 23995500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 27015500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 24001000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 27016500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 204033500 # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks 116 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 116 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks 608 # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total 608 # number of WritebackClean accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59510.791367 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59514.388489 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59510.791367 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59514.388489 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 59512.589928 # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59513.647643 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59527.295285 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59542.183623 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 59555.831266 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 59534.739454 # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59503.174603 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59503.174603 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59503.174603 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59504.761905 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 59503.571429 # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 59513.647643 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 59505.506608 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 59527.295285 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 59506.607930 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 59542.183623 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 59505.506608 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 59555.831266 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 59507.709251 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 59519.690782 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 59513.647643 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 59505.506608 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 59527.295285 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 59506.607930 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 59542.183623 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 59505.506608 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 59555.831266 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 59507.709251 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 59519.690782 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 403 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 403 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 403 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 403 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total 1612 # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data 315 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 315 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data 315 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data 315 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 1260 # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 3428 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6882000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6882500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 6882000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 6882500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 27529000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 19954000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 19959500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 19965500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 19971000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total 79850000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 15593500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 15593500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 15593500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 15594000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 62374500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 19954000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 22475500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 19959500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 22476000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 19965500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 22475500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 19971000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 22476500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 169753500 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 19954000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 22475500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 19959500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 22476000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 19965500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 22475500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 19971000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 22476500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 169753500 # number of overall MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49510.791367 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49514.388489 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49510.791367 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49514.388489 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 49512.589928 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49534.739454 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49503.174603 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49503.174603 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49503.174603 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49504.761905 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49503.571429 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49505.506608 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49506.607930 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49505.506608 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49505.506608 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49506.607930 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49505.506608 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3442 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3442 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3442 # Request fanout histogram
-system.membus.reqLayer0.occupancy 3471468 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 17140000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3704 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 3704 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3704 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3002000 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:24
-gem5 executing on ribera.cs.wisc.edu, pid 29045
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:28
+gem5 executing on zizzer, pid 26163
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2820224 # Simulator instruction rate (inst/s)
-host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1410112599 # Simulator tick rate (ticks/s)
-host_mem_usage 285836 # Number of bytes of host memory used
-host_seconds 141.36 # Real time elapsed on the host
+host_inst_rate 1206963 # Simulator instruction rate (inst/s)
+host_op_rate 1206963 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 603481628 # Simulator tick rate (ticks/s)
+host_mem_usage 226620 # Number of bytes of host memory used
+host_seconds 330.30 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
-system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
-system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
-system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
-system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 566939869 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664651 # Class of executed instruction
+system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
+system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
+system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
+system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
+system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 566939869 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:21
-gem5 executing on ribera.cs.wisc.edu, pid 7757
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:38
+gem5 executing on zizzer, pid 881
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 107836000 # Number of ticks simulated
final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71421 # Simulator instruction rate (inst/s)
-host_op_rate 71421 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7746922 # Simulator tick rate (ticks/s)
-host_mem_usage 306188 # Number of bytes of host memory used
-host_seconds 13.92 # Real time elapsed on the host
+host_inst_rate 74115 # Simulator instruction rate (inst/s)
+host_op_rate 74115 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8039101 # Simulator tick rate (ticks/s)
+host_mem_usage 247436 # Number of bytes of host memory used
+host_seconds 13.41 # Real time elapsed on the host
sim_insts 994171 # Number of instructions simulated
sim_ops 994171 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:11
-gem5 executing on ribera.cs.wisc.edu, pid 7751
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:39
+gem5 executing on zizzer, pid 893
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 158878 # Simulator instruction rate (inst/s)
-host_op_rate 158877 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20572695 # Simulator tick rate (ticks/s)
-host_mem_usage 302096 # Number of bytes of host memory used
+host_inst_rate 159037 # Simulator instruction rate (inst/s)
+host_op_rate 159036 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20593264 # Simulator tick rate (ticks/s)
+host_mem_usage 242980 # Number of bytes of host memory used
host_seconds 4.26 # Real time elapsed on the host
sim_insts 677333 # Number of instructions simulated
sim_ops 677333 # Number of ops (including micro ops) simulated
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:11
-gem5 executing on ribera.cs.wisc.edu, pid 7748
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:37
+gem5 executing on zizzer, pid 872
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 264840500 # Number of ticks simulated
final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 154084 # Simulator instruction rate (inst/s)
-host_op_rate 154083 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 61608375 # Simulator tick rate (ticks/s)
-host_mem_usage 302100 # Number of bytes of host memory used
-host_seconds 4.30 # Real time elapsed on the host
+host_inst_rate 139043 # Simulator instruction rate (inst/s)
+host_op_rate 139043 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55594555 # Simulator tick rate (ticks/s)
+host_mem_usage 242988 # Number of bytes of host memory used
+host_seconds 4.76 # Real time elapsed on the host
sim_insts 662366 # Number of instructions simulated
sim_ops 662366 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl1.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl2.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl3.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl4.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl5.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl6.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl7.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:41:13
-gem5 started Nov 15 2015 14:41:38
-gem5 executing on ribera.cs.wisc.edu, pid 32150
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
+gem5 compiled Dec 11 2015 20:05:44
+gem5 started Dec 11 2015 20:06:16
+gem5 executing on zizzer, pid 37021
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 10021833 # Number of ticks simulated
final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 133555 # Simulator tick rate (ticks/s)
-host_mem_usage 453936 # Number of bytes of host memory used
-host_seconds 75.04 # Real time elapsed on the host
+host_tick_rate 77650 # Simulator tick rate (ticks/s)
+host_mem_usage 393812 # Number of bytes of host memory used
+host_seconds 129.06 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl1.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl2.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl3.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl4.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl5.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl6.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl7.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:46:21
-gem5 started Nov 15 2015 14:46:44
-gem5 executing on ribera.cs.wisc.edu, pid 1171
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
+gem5 compiled Dec 11 2015 20:10:49
+gem5 started Dec 11 2015 20:11:27
+gem5 executing on zizzer, pid 42472
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 7436579 # Number of ticks simulated
final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 57999 # Simulator tick rate (ticks/s)
-host_mem_usage 456048 # Number of bytes of host memory used
-host_seconds 128.22 # Real time elapsed on the host
+host_tick_rate 35364 # Simulator tick rate (ticks/s)
+host_mem_usage 396444 # Number of bytes of host memory used
+host_seconds 210.29 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl1.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl2.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl3.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl4.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl5.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl6.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl7.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:51:28
-gem5 started Nov 15 2015 14:51:57
-gem5 executing on ribera.cs.wisc.edu, pid 2898
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
+gem5 compiled Dec 11 2015 20:15:50
+gem5 started Dec 11 2015 20:16:20
+gem5 executing on zizzer, pid 47643
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 6099346 # Number of ticks simulated
final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 63389 # Simulator tick rate (ticks/s)
-host_mem_usage 457160 # Number of bytes of host memory used
-host_seconds 96.22 # Real time elapsed on the host
+host_tick_rate 38144 # Simulator tick rate (ticks/s)
+host_mem_usage 397068 # Number of bytes of host memory used
+host_seconds 159.90 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl1.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl2.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl3.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl4.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl5.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl6.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl7.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:35:53
-gem5 started Nov 15 2015 14:36:14
-gem5 executing on ribera.cs.wisc.edu, pid 30618
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
+gem5 compiled Dec 11 2015 20:00:36
+gem5 started Dec 11 2015 20:01:07
+gem5 executing on zizzer, pid 31717
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 4722948 # Number of ticks simulated
final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 44680 # Simulator tick rate (ticks/s)
-host_mem_usage 457072 # Number of bytes of host memory used
-host_seconds 105.71 # Real time elapsed on the host
+host_tick_rate 25861 # Simulator tick rate (ticks/s)
+host_mem_usage 397392 # Number of bytes of host memory used
+host_seconds 182.63 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl1.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl2.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl3.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl4.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl5.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl6.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
icache=system.ruby.l1_cntrl7.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:38
-gem5 executing on ribera.cs.wisc.edu, pid 29108
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:41
+gem5 executing on zizzer, pid 26230
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 7678882 # Number of ticks simulated
final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 112166 # Simulator tick rate (ticks/s)
-host_mem_usage 452656 # Number of bytes of host memory used
-host_seconds 68.46 # Real time elapsed on the host
+host_tick_rate 64715 # Simulator tick rate (ticks/s)
+host_mem_usage 392924 # Number of bytes of host memory used
+host_seconds 118.66 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory
-Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:58:33
-gem5 started Nov 15 2015 14:58:44
-gem5 executing on ribera.cs.wisc.edu, pid 5046
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /scratch/nilay/GEM5/gem5/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter
+gem5 compiled Dec 11 2015 20:23:08
+gem5 started Dec 11 2015 20:23:21
+gem5 executing on zizzer, pid 55319
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 540820000 # Number of ticks simulated
final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 74356212 # Simulator tick rate (ticks/s)
-host_mem_usage 274932 # Number of bytes of host memory used
-host_seconds 7.27 # Real time elapsed on the host
+host_tick_rate 45415693 # Simulator tick rate (ticks/s)
+host_mem_usage 216096 # Number of bytes of host memory used
+host_seconds 11.91 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory
-Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:58:33
-gem5 started Nov 15 2015 14:58:45
-gem5 executing on ribera.cs.wisc.edu, pid 5047
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /scratch/nilay/GEM5/gem5/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest
+gem5 compiled Dec 11 2015 20:23:08
+gem5 started Dec 11 2015 20:23:21
+gem5 executing on zizzer, pid 55313
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 534039500 # Number of ticks simulated
final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 75793857 # Simulator tick rate (ticks/s)
-host_mem_usage 274932 # Number of bytes of host memory used
-host_seconds 7.05 # Real time elapsed on the host
+host_tick_rate 46247904 # Simulator tick rate (ticks/s)
+host_mem_usage 215924 # Number of bytes of host memory used
+host_seconds 11.55 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:48
-gem5 executing on ribera.cs.wisc.edu, pid 29078
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26143
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2813944 # Simulator instruction rate (inst/s)
-host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1408584494 # Simulator tick rate (ticks/s)
-host_mem_usage 287952 # Number of bytes of host memory used
-host_seconds 31.39 # Real time elapsed on the host
+host_inst_rate 1163222 # Simulator instruction rate (inst/s)
+host_op_rate 1163221 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 582277557 # Simulator tick rate (ticks/s)
+host_mem_usage 229020 # Number of bytes of host memory used
+host_seconds 75.95 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
-system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
-system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
-system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
-system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 123328088 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
+system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
+system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
+system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
+system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
+system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 123328088 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:37
-gem5 executing on ribera.cs.wisc.edu, pid 29068
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:28
+gem5 executing on zizzer, pid 26157
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 134741611500 # Number of ticks simulated
final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 947641 # Simulator instruction rate (inst/s)
-host_op_rate 947641 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1445388793 # Simulator tick rate (ticks/s)
-host_mem_usage 301064 # Number of bytes of host memory used
-host_seconds 93.22 # Real time elapsed on the host
+host_inst_rate 541440 # Simulator instruction rate (inst/s)
+host_op_rate 541439 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 825830456 # Simulator tick rate (ticks/s)
+host_mem_usage 239292 # Number of bytes of host memory used
+host_seconds 163.16 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:25:11
-gem5 executing on ribera.cs.wisc.edu, pid 11028
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:10
+gem5 executing on zizzer, pid 11551
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 48960011500 # Number of ticks simulated
final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1012333 # Simulator instruction rate (inst/s)
-host_op_rate 1294633 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 698936270 # Simulator tick rate (ticks/s)
-host_mem_usage 308028 # Number of bytes of host memory used
-host_seconds 70.05 # Real time elapsed on the host
+host_inst_rate 581361 # Simulator instruction rate (inst/s)
+host_op_rate 743480 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 401384017 # Simulator tick rate (ticks/s)
+host_mem_usage 246028 # Number of bytes of host memory used
+host_seconds 121.98 # Real time elapsed on the host
sim_insts 70913182 # Number of instructions simulated
sim_ops 90688137 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:29:25
-gem5 executing on ribera.cs.wisc.edu, pid 11171
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:10
+gem5 executing on zizzer, pid 11561
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 128076812500 # Number of ticks simulated
final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 552478 # Simulator instruction rate (inst/s)
-host_op_rate 705359 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1005483876 # Simulator tick rate (ticks/s)
-host_mem_usage 318020 # Number of bytes of host memory used
-host_seconds 127.38 # Real time elapsed on the host
+host_inst_rate 359737 # Simulator instruction rate (inst/s)
+host_op_rate 459283 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 654705413 # Simulator tick rate (ticks/s)
+host_mem_usage 256212 # Number of bytes of host memory used
+host_seconds 195.63 # Real time elapsed on the host
sim_insts 70373629 # Number of instructions simulated
sim_ops 89847363 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:27
-gem5 executing on ribera.cs.wisc.edu, pid 7787
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:40
+gem5 executing on zizzer, pid 899
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2078407 # Simulator instruction rate (inst/s)
-host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1053881878 # Simulator tick rate (ticks/s)
-host_mem_usage 288492 # Number of bytes of host memory used
-host_seconds 64.66 # Real time elapsed on the host
+host_inst_rate 1114079 # Simulator instruction rate (inst/s)
+host_op_rate 1128504 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 564907393 # Simulator tick rate (ticks/s)
+host_mem_usage 228612 # Number of bytes of host memory used
+host_seconds 120.64 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
-system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
-system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
-system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
-system.membus.trans_dist::SwapReq 15916 # Transaction distribution
-system.membus.trans_dist::SwapResp 15916 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
-system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 192665090 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297345 # number of cpu cycles simulated
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293798 # Class of executed instruction
+system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
+system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
+system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
+system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
+system.membus.trans_dist::SwapReq 15916 # Transaction distribution
+system.membus.trans_dist::SwapResp 15916 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
+system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 192665090 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:22
-gem5 executing on ribera.cs.wisc.edu, pid 7773
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:39
+gem5 executing on zizzer, pid 896
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 203115876500 # Number of ticks simulated
final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 826258 # Simulator instruction rate (inst/s)
-host_op_rate 836957 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1248716263 # Simulator tick rate (ticks/s)
-host_mem_usage 299980 # Number of bytes of host memory used
-host_seconds 162.66 # Real time elapsed on the host
+host_inst_rate 554782 # Simulator instruction rate (inst/s)
+host_op_rate 561966 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 838437229 # Simulator tick rate (ticks/s)
+host_mem_usage 239012 # Number of bytes of host memory used
+host_seconds 242.26 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l1_cntrl0.unblockFromL1Cache]
type=MessageBuffer
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:41:13
-gem5 started Nov 15 2015 14:41:38
-gem5 executing on ribera.cs.wisc.edu, pid 32148
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
+gem5 compiled Dec 11 2015 20:05:44
+gem5 started Dec 11 2015 20:06:16
+gem5 executing on zizzer, pid 37019
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 41751 because Ruby Tester completed
+Exiting @ tick 43191 because Ruby Tester completed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000042 # Number of seconds simulated
-sim_ticks 41751 # Number of ticks simulated
-final_tick 41751 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000043 # Number of seconds simulated
+sim_ticks 43191 # Number of ticks simulated
+final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 456955 # Simulator tick rate (ticks/s)
-host_mem_usage 445744 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 266014 # Simulator tick rate (ticks/s)
+host_mem_usage 386184 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55552 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55552 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49728 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49728 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 868 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 868 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 777 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 777 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1330554957 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1330554957 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1191061292 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1191061292 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2521616249 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2521616249 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 868 # Number of read requests accepted
-system.mem_ctrls.writeReqs 777 # Number of write requests accepted
-system.mem_ctrls.readBursts 868 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 777 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9792 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55552 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49728 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 123 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 57728 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 51904 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 51904 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 902 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 902 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 811 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 811 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1336574749 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1336574749 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1201731842 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1201731842 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 2538306592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 2538306592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 902 # Number of read requests accepted
+system.mem_ctrls.writeReqs 811 # Number of write requests accepted
+system.mem_ctrls.readBursts 902 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 811 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 47168 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 57728 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 51904 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 130 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 213 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 219 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 227 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 48 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 191 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 198 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 201 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 46 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 41665 # Total gap between requests
+system.mem_ctrls.totGap 43109 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 868 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 902 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 777 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 439 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 276 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 811 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 456 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 281 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 943.460674 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 892.281841 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 207.277759 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 1 1.12% 1.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 1 1.12% 2.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 6.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3 3.37% 10.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 4.49% 14.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 6 6.74% 21.35% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 70 78.65% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 18.128205 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.885323 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.442608 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 4 10.26% 10.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 17 43.59% 53.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 12 30.77% 84.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 89.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 3 7.69% 97.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 2.56% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.205128 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.194457 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.614709 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 35 89.74% 89.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 4 10.26% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8953 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 22538 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.52 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 928 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 868.246553 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 227.729324 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 1 1.06% 1.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 2 2.13% 3.19% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 3 3.19% 6.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 1 1.06% 7.45% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 4 4.26% 11.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 3 3.19% 14.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 17.02% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 3.19% 20.21% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 75 79.79% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 18.125000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.875881 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.480256 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 4 10.00% 10.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 17 42.50% 52.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 12 30.00% 82.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 87.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 3 7.50% 95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-25 1 2.50% 97.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.280005 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.853349 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 1 2.50% 90.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 3 7.50% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 8956 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 22959 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3685 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.15 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.52 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1096.02 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 968.79 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1330.55 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1191.06 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.15 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1092.08 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 966.13 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1336.57 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1201.73 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 16.13 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 8.56 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 7.57 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.65 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.68 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 630 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 624 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 88.11 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.41 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 25.33 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.60 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls.busUtil 16.08 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 8.53 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 7.55 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.63 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 25.46 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 647 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 644 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.79 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 94.57 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 25.17 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 665280 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 369600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 8311680 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 6034176 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6231168 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 26710200 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 26706780 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 44685456 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1140.080520 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 44914308 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1146.065527 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 37890 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 37885 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 6487 # delay histogram for all message
-system.ruby.delayHist::mean 2.607369 # delay histogram for all message
-system.ruby.delayHist::stdev 5.331776 # delay histogram for all message
-system.ruby.delayHist | 4997 77.03% 77.03% | 72 1.11% 78.14% | 1050 16.19% 94.33% | 14 0.22% 94.54% | 300 4.62% 99.17% | 2 0.03% 99.20% | 2 0.03% 99.23% | 47 0.72% 99.95% | 0 0.00% 99.95% | 3 0.05% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 6487 # delay histogram for all message
+system.ruby.delayHist::samples 6720 # delay histogram for all message
+system.ruby.delayHist::mean 2.675000 # delay histogram for all message
+system.ruby.delayHist::stdev 5.399947 # delay histogram for all message
+system.ruby.delayHist | 5144 76.55% 76.55% | 51 0.76% 77.31% | 1138 16.93% 94.24% | 8 0.12% 94.36% | 323 4.81% 99.17% | 6 0.09% 99.26% | 0 0.00% 99.26% | 43 0.64% 99.90% | 0 0.00% 99.90% | 7 0.10% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 6720 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 988
-system.ruby.outstanding_req_hist::mean 15.694332
-system.ruby.outstanding_req_hist::gmean 15.587555
-system.ruby.outstanding_req_hist::stdev 1.214439
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.40% 1.11% | 2 0.20% 1.32% | 5 0.51% 1.82% | 157 15.89% 17.71% | 813 82.29% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 988
+system.ruby.outstanding_req_hist::samples 1041
+system.ruby.outstanding_req_hist::mean 15.700288
+system.ruby.outstanding_req_hist::gmean 15.598621
+system.ruby.outstanding_req_hist::stdev 1.186661
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.48% | 2 0.19% 0.67% | 4 0.38% 1.06% | 2 0.19% 1.25% | 5 0.48% 1.73% | 167 16.04% 17.77% | 856 82.23% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 1041
system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 973
-system.ruby.latency_hist::mean 670.474820
-system.ruby.latency_hist::gmean 404.512965
-system.ruby.latency_hist::stdev 282.511489
-system.ruby.latency_hist | 123 12.64% 12.64% | 25 2.57% 15.21% | 6 0.62% 15.83% | 4 0.41% 16.24% | 32 3.29% 19.53% | 325 33.40% 52.93% | 378 38.85% 91.78% | 43 4.42% 96.20% | 29 2.98% 99.18% | 8 0.82% 100.00%
-system.ruby.latency_hist::total 973
+system.ruby.latency_hist::samples 1025
+system.ruby.latency_hist::mean 658.597073
+system.ruby.latency_hist::gmean 361.484818
+system.ruby.latency_hist::stdev 297.350955
+system.ruby.latency_hist | 154 15.02% 15.02% | 24 2.34% 17.37% | 5 0.49% 17.85% | 4 0.39% 18.24% | 32 3.12% 21.37% | 302 29.46% 50.83% | 418 40.78% 91.61% | 49 4.78% 96.39% | 28 2.73% 99.12% | 9 0.88% 100.00%
+system.ruby.latency_hist::total 1025
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 67
+system.ruby.hit_latency_hist::samples 89
system.ruby.hit_latency_hist::mean 1
system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 67 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 67
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 89
system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 906
-system.ruby.miss_latency_hist::mean 719.983444
-system.ruby.miss_latency_hist::gmean 630.548999
-system.ruby.miss_latency_hist::stdev 223.799725
-system.ruby.miss_latency_hist | 56 6.18% 6.18% | 25 2.76% 8.94% | 6 0.66% 9.60% | 4 0.44% 10.04% | 32 3.53% 13.58% | 325 35.87% 49.45% | 378 41.72% 91.17% | 43 4.75% 95.92% | 29 3.20% 99.12% | 8 0.88% 100.00%
-system.ruby.miss_latency_hist::total 906
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 66 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 936
+system.ruby.miss_latency_hist::mean 721.125000
+system.ruby.miss_latency_hist::gmean 632.888578
+system.ruby.miss_latency_hist::stdev 227.503250
+system.ruby.miss_latency_hist | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00%
+system.ruby.miss_latency_hist::total 936
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 89 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 964 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 64 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 64 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 88 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
-system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 868 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 906 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 34 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 904 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 938 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 11.787742
-system.ruby.network.routers0.msg_count.Control::0 908
-system.ruby.network.routers0.msg_count.Request_Control::2 264
-system.ruby.network.routers0.msg_count.Response_Data::1 906
-system.ruby.network.routers0.msg_count.Response_Control::1 831
-system.ruby.network.routers0.msg_count.Response_Control::2 850
-system.ruby.network.routers0.msg_count.Writeback_Data::0 745
-system.ruby.network.routers0.msg_count.Writeback_Data::1 215
-system.ruby.network.routers0.msg_count.Writeback_Control::0 39
-system.ruby.network.routers0.msg_bytes.Control::0 7264
-system.ruby.network.routers0.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers0.msg_bytes.Response_Data::1 65232
-system.ruby.network.routers0.msg_bytes.Response_Control::1 6648
-system.ruby.network.routers0.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 312
-system.ruby.network.routers1.percent_links_utilized 21.738401
-system.ruby.network.routers1.msg_count.Control::0 1774
-system.ruby.network.routers1.msg_count.Request_Control::2 264
-system.ruby.network.routers1.msg_count.Response_Data::1 2551
-system.ruby.network.routers1.msg_count.Response_Control::1 1782
-system.ruby.network.routers1.msg_count.Response_Control::2 850
-system.ruby.network.routers1.msg_count.Writeback_Data::0 745
-system.ruby.network.routers1.msg_count.Writeback_Data::1 215
-system.ruby.network.routers1.msg_count.Writeback_Control::0 38
-system.ruby.network.routers1.msg_bytes.Control::0 14192
-system.ruby.network.routers1.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers1.msg_bytes.Response_Data::1 183672
-system.ruby.network.routers1.msg_bytes.Response_Control::1 14256
-system.ruby.network.routers1.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 304
-system.ruby.network.routers2.percent_links_utilized 9.954253
-system.ruby.network.routers2.msg_count.Control::0 868
-system.ruby.network.routers2.msg_count.Response_Data::1 1645
-system.ruby.network.routers2.msg_count.Response_Control::1 951
-system.ruby.network.routers2.msg_bytes.Control::0 6944
-system.ruby.network.routers2.msg_bytes.Response_Data::1 118440
-system.ruby.network.routers2.msg_bytes.Response_Control::1 7608
-system.ruby.network.routers3.percent_links_utilized 14.493864
-system.ruby.network.routers3.msg_count.Control::0 1775
-system.ruby.network.routers3.msg_count.Request_Control::2 264
-system.ruby.network.routers3.msg_count.Response_Data::1 2551
-system.ruby.network.routers3.msg_count.Response_Control::1 1782
-system.ruby.network.routers3.msg_count.Response_Control::2 850
-system.ruby.network.routers3.msg_count.Writeback_Data::0 745
-system.ruby.network.routers3.msg_count.Writeback_Data::1 215
-system.ruby.network.routers3.msg_count.Writeback_Control::0 38
-system.ruby.network.routers3.msg_bytes.Control::0 14200
-system.ruby.network.routers3.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers3.msg_bytes.Response_Data::1 183672
-system.ruby.network.routers3.msg_bytes.Response_Control::1 14256
-system.ruby.network.routers3.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 304
-system.ruby.network.msg_count.Control 5325
-system.ruby.network.msg_count.Request_Control 792
-system.ruby.network.msg_count.Response_Data 7653
-system.ruby.network.msg_count.Response_Control 7896
-system.ruby.network.msg_count.Writeback_Data 2880
-system.ruby.network.msg_count.Writeback_Control 115
-system.ruby.network.msg_byte.Control 42600
-system.ruby.network.msg_byte.Request_Control 6336
-system.ruby.network.msg_byte.Response_Data 551016
-system.ruby.network.msg_byte.Response_Control 63168
-system.ruby.network.msg_byte.Writeback_Data 207360
-system.ruby.network.msg_byte.Writeback_Control 920
-system.ruby.network.routers0.throttle0.link_utilization 11.017700
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 264
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 906
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 782
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 65232
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6256
-system.ruby.network.routers0.throttle1.link_utilization 12.557783
-system.ruby.network.routers0.throttle1.msg_count.Control::0 908
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 49
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 850
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 745
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 215
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 39
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7264
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 392
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 312
-system.ruby.network.routers1.throttle0.link_utilization 22.940768
-system.ruby.network.routers1.throttle0.msg_count.Control::0 906
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 868
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 913
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 850
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 745
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 215
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 38
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7248
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62496
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7304
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 304
-system.ruby.network.routers1.throttle1.link_utilization 20.536035
-system.ruby.network.routers1.throttle1.msg_count.Control::0 868
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 264
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1683
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 869
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6944
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 121176
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6952
-system.ruby.network.routers2.throttle0.link_utilization 9.518335
-system.ruby.network.routers2.throttle0.msg_count.Control::0 868
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 777
+system.ruby.network.routers0.percent_links_utilized 11.804543
+system.ruby.network.routers0.msg_count.Control::0 939
+system.ruby.network.routers0.msg_count.Request_Control::2 278
+system.ruby.network.routers0.msg_count.Response_Data::1 936
+system.ruby.network.routers0.msg_count.Response_Control::1 873
+system.ruby.network.routers0.msg_count.Response_Control::2 873
+system.ruby.network.routers0.msg_count.Writeback_Data::0 785
+system.ruby.network.routers0.msg_count.Writeback_Data::1 213
+system.ruby.network.routers0.msg_count.Writeback_Control::0 25
+system.ruby.network.routers0.msg_bytes.Control::0 7512
+system.ruby.network.routers0.msg_bytes.Request_Control::2 2224
+system.ruby.network.routers0.msg_bytes.Response_Data::1 67392
+system.ruby.network.routers0.msg_bytes.Response_Control::1 6984
+system.ruby.network.routers0.msg_bytes.Response_Control::2 6984
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 56520
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15336
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers1.percent_links_utilized 21.822255
+system.ruby.network.routers1.msg_count.Control::0 1842
+system.ruby.network.routers1.msg_count.Request_Control::2 279
+system.ruby.network.routers1.msg_count.Response_Data::1 2649
+system.ruby.network.routers1.msg_count.Response_Control::1 1859
+system.ruby.network.routers1.msg_count.Response_Control::2 873
+system.ruby.network.routers1.msg_count.Writeback_Data::0 785
+system.ruby.network.routers1.msg_count.Writeback_Data::1 213
+system.ruby.network.routers1.msg_count.Writeback_Control::0 25
+system.ruby.network.routers1.msg_bytes.Control::0 14736
+system.ruby.network.routers1.msg_bytes.Request_Control::2 2232
+system.ruby.network.routers1.msg_bytes.Response_Data::1 190728
+system.ruby.network.routers1.msg_bytes.Response_Control::1 14872
+system.ruby.network.routers1.msg_bytes.Response_Control::2 6984
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0 56520
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15336
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers2.percent_links_utilized 10.015976
+system.ruby.network.routers2.msg_count.Control::0 902
+system.ruby.network.routers2.msg_count.Response_Data::1 1713
+system.ruby.network.routers2.msg_count.Response_Control::1 985
+system.ruby.network.routers2.msg_bytes.Control::0 7216
+system.ruby.network.routers2.msg_bytes.Response_Data::1 123336
+system.ruby.network.routers2.msg_bytes.Response_Control::1 7880
+system.ruby.network.routers3.percent_links_utilized 14.547012
+system.ruby.network.routers3.msg_count.Control::0 1841
+system.ruby.network.routers3.msg_count.Request_Control::2 278
+system.ruby.network.routers3.msg_count.Response_Data::1 2649
+system.ruby.network.routers3.msg_count.Response_Control::1 1858
+system.ruby.network.routers3.msg_count.Response_Control::2 873
+system.ruby.network.routers3.msg_count.Writeback_Data::0 785
+system.ruby.network.routers3.msg_count.Writeback_Data::1 213
+system.ruby.network.routers3.msg_count.Writeback_Control::0 25
+system.ruby.network.routers3.msg_bytes.Control::0 14728
+system.ruby.network.routers3.msg_bytes.Request_Control::2 2224
+system.ruby.network.routers3.msg_bytes.Response_Data::1 190728
+system.ruby.network.routers3.msg_bytes.Response_Control::1 14864
+system.ruby.network.routers3.msg_bytes.Response_Control::2 6984
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0 56520
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15336
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 200
+system.ruby.network.msg_count.Control 5524
+system.ruby.network.msg_count.Request_Control 835
+system.ruby.network.msg_count.Response_Data 7947
+system.ruby.network.msg_count.Response_Control 8194
+system.ruby.network.msg_count.Writeback_Data 2994
+system.ruby.network.msg_count.Writeback_Control 75
+system.ruby.network.msg_byte.Control 44192
+system.ruby.network.msg_byte.Request_Control 6680
+system.ruby.network.msg_byte.Response_Data 572184
+system.ruby.network.msg_byte.Response_Control 65552
+system.ruby.network.msg_byte.Writeback_Data 215568
+system.ruby.network.msg_byte.Writeback_Control 600
+system.ruby.network.routers0.throttle0.link_utilization 11.009238
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 278
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 936
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 808
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2224
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 67392
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6464
+system.ruby.network.routers0.throttle1.link_utilization 12.599847
+system.ruby.network.routers0.throttle1.msg_count.Control::0 939
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 65
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 873
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 785
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 213
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 25
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7512
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 520
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6984
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 56520
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15336
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers1.throttle0.link_utilization 23.037207
+system.ruby.network.routers1.throttle0.msg_count.Control::0 939
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 902
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 963
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 873
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 785
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 213
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 25
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7512
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 64944
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7704
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6984
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 56520
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15336
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers1.throttle1.link_utilization 20.607302
+system.ruby.network.routers1.throttle1.msg_count.Control::0 903
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 279
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1747
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 896
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0 7224
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2232
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 125784
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 7168
+system.ruby.network.routers2.throttle0.link_utilization 9.594591
+system.ruby.network.routers2.throttle0.msg_count.Control::0 902
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 811
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 87
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6944
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 55944
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0 7216
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 58392
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 696
-system.ruby.network.routers2.throttle1.link_utilization 10.390170
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 868
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 864
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62496
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6912
-system.ruby.network.routers3.throttle0.link_utilization 11.017700
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 264
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 906
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 782
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2112
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 65232
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6256
-system.ruby.network.routers3.throttle1.link_utilization 22.945558
-system.ruby.network.routers3.throttle1.msg_count.Control::0 907
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 868
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 913
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 850
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 745
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 215
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 38
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7256
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62496
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7304
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6800
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 53640
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15480
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 304
-system.ruby.network.routers3.throttle2.link_utilization 9.518335
-system.ruby.network.routers3.throttle2.msg_count.Control::0 868
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 777
+system.ruby.network.routers2.throttle1.link_utilization 10.437360
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 902
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 898
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 64944
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 7184
+system.ruby.network.routers3.throttle0.link_utilization 11.009238
+system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 278
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 936
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 808
+system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2224
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 67392
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6464
+system.ruby.network.routers3.throttle1.link_utilization 23.037207
+system.ruby.network.routers3.throttle1.msg_count.Control::0 939
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 902
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 963
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 873
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 785
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 213
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 25
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7512
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 64944
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7704
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6984
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 56520
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15336
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers3.throttle2.link_utilization 9.594591
+system.ruby.network.routers3.throttle2.msg_count.Control::0 902
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 811
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 87
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6944
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 55944
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0 7216
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 58392
system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 696
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 2539 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 5.571485 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 7.083143 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 1391 54.79% 54.79% | 17 0.67% 55.45% | 768 30.25% 85.70% | 9 0.35% 86.06% | 300 11.82% 97.87% | 2 0.08% 97.95% | 2 0.08% 98.03% | 47 1.85% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 2539 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 3684 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.750271 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 2.345078 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 3317 90.04% 90.04% | 25 0.68% 90.72% | 16 0.43% 91.15% | 39 1.06% 92.21% | 232 6.30% 98.51% | 50 1.36% 99.86% | 5 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 3684 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_0::samples 2620 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean 5.712977 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 7.142048 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 1406 53.66% 53.66% | 9 0.34% 54.01% | 823 31.41% 85.42% | 4 0.15% 85.57% | 323 12.33% 97.90% | 5 0.19% 98.09% | 0 0.00% 98.09% | 43 1.64% 99.73% | 0 0.00% 99.73% | 7 0.27% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 2620 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 3822 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.787023 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 2.428600 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 3460 90.53% 90.53% | 42 1.10% 91.63% | 315 8.24% 99.87% | 4 0.10% 99.97% | 0 0.00% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 3822 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 264 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.015152 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.173746 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 262 99.24% 99.24% | 0 0.00% 99.24% | 2 0.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 264 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 278 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 278 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 278 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
-system.ruby.LD.latency_hist::samples 43
-system.ruby.LD.latency_hist::mean 744.930233
-system.ruby.LD.latency_hist::gmean 498.811687
-system.ruby.LD.latency_hist::stdev 228.289227
-system.ruby.LD.latency_hist | 3 6.98% 6.98% | 0 0.00% 6.98% | 0 0.00% 6.98% | 0 0.00% 6.98% | 1 2.33% 9.30% | 15 34.88% 44.19% | 20 46.51% 90.70% | 1 2.33% 93.02% | 3 6.98% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 43
+system.ruby.LD.latency_hist::samples 37
+system.ruby.LD.latency_hist::mean 621.135135
+system.ruby.LD.latency_hist::gmean 207.168110
+system.ruby.LD.latency_hist::stdev 333.448910
+system.ruby.LD.latency_hist | 8 21.62% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 13 35.14% 56.76% | 14 37.84% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist::total 37
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
-system.ruby.LD.hit_latency_hist::samples 3
+system.ruby.LD.hit_latency_hist::samples 7
system.ruby.LD.hit_latency_hist::mean 1
system.ruby.LD.hit_latency_hist::gmean 1
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 3
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 7
system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
-system.ruby.LD.miss_latency_hist::samples 40
-system.ruby.LD.miss_latency_hist::mean 800.725000
-system.ruby.LD.miss_latency_hist::gmean 794.843938
-system.ruby.LD.miss_latency_hist::stdev 101.785594
-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.50% 2.50% | 15 37.50% 40.00% | 20 50.00% 90.00% | 1 2.50% 92.50% | 3 7.50% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 40
+system.ruby.LD.miss_latency_hist::samples 30
+system.ruby.LD.miss_latency_hist::mean 765.833333
+system.ruby.LD.miss_latency_hist::gmean 719.114834
+system.ruby.LD.miss_latency_hist::stdev 153.429099
+system.ruby.LD.miss_latency_hist | 1 3.33% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 13 43.33% 46.67% | 14 46.67% 93.33% | 2 6.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 30
system.ruby.ST.latency_hist::bucket_size 128
system.ruby.ST.latency_hist::max_bucket 1279
-system.ruby.ST.latency_hist::samples 873
-system.ruby.ST.latency_hist::mean 703.712486
-system.ruby.ST.latency_hist::gmean 443.583948
-system.ruby.ST.latency_hist::stdev 252.870649
-system.ruby.ST.latency_hist | 83 9.51% 9.51% | 7 0.80% 10.31% | 4 0.46% 10.77% | 4 0.46% 11.23% | 31 3.55% 14.78% | 310 35.51% 50.29% | 358 41.01% 91.29% | 42 4.81% 96.11% | 26 2.98% 99.08% | 8 0.92% 100.00%
-system.ruby.ST.latency_hist::total 873
+system.ruby.ST.latency_hist::samples 925
+system.ruby.ST.latency_hist::mean 697.631351
+system.ruby.ST.latency_hist::gmean 404.802159
+system.ruby.ST.latency_hist::stdev 266.794551
+system.ruby.ST.latency_hist | 101 10.92% 10.92% | 7 0.76% 11.68% | 4 0.43% 12.11% | 4 0.43% 12.54% | 32 3.46% 16.00% | 289 31.24% 47.24% | 404 43.68% 90.92% | 47 5.08% 96.00% | 28 3.03% 99.03% | 9 0.97% 100.00%
+system.ruby.ST.latency_hist::total 925
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
-system.ruby.ST.hit_latency_hist::samples 63
+system.ruby.ST.hit_latency_hist::samples 82
system.ruby.ST.hit_latency_hist::mean 1
system.ruby.ST.hit_latency_hist::gmean 1
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 63 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 63
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 82 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 82
system.ruby.ST.miss_latency_hist::bucket_size 128
system.ruby.ST.miss_latency_hist::max_bucket 1279
-system.ruby.ST.miss_latency_hist::samples 810
-system.ruby.ST.miss_latency_hist::mean 758.367901
-system.ruby.ST.miss_latency_hist::gmean 712.609684
-system.ruby.ST.miss_latency_hist::stdev 165.763918
-system.ruby.ST.miss_latency_hist | 20 2.47% 2.47% | 7 0.86% 3.33% | 4 0.49% 3.83% | 4 0.49% 4.32% | 31 3.83% 8.15% | 310 38.27% 46.42% | 358 44.20% 90.62% | 42 5.19% 95.80% | 26 3.21% 99.01% | 8 0.99% 100.00%
-system.ruby.ST.miss_latency_hist::total 810
+system.ruby.ST.miss_latency_hist::samples 843
+system.ruby.ST.miss_latency_hist::mean 765.393832
+system.ruby.ST.miss_latency_hist::gmean 725.861277
+system.ruby.ST.miss_latency_hist::stdev 162.026380
+system.ruby.ST.miss_latency_hist | 19 2.25% 2.25% | 7 0.83% 3.08% | 4 0.47% 3.56% | 4 0.47% 4.03% | 32 3.80% 7.83% | 289 34.28% 42.11% | 404 47.92% 90.04% | 47 5.58% 95.61% | 28 3.32% 98.93% | 9 1.07% 100.00%
+system.ruby.ST.miss_latency_hist::total 843
system.ruby.IFETCH.latency_hist::bucket_size 64
system.ruby.IFETCH.latency_hist::max_bucket 639
-system.ruby.IFETCH.latency_hist::samples 57
-system.ruby.IFETCH.latency_hist::mean 105.245614
-system.ruby.IFETCH.latency_hist::gmean 84.136461
-system.ruby.IFETCH.latency_hist::stdev 62.237816
-system.ruby.IFETCH.latency_hist | 15 26.32% 26.32% | 22 38.60% 64.91% | 16 28.07% 92.98% | 2 3.51% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 57
-system.ruby.IFETCH.hit_latency_hist::bucket_size 1
-system.ruby.IFETCH.hit_latency_hist::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist::samples 1
-system.ruby.IFETCH.hit_latency_hist::mean 1
-system.ruby.IFETCH.hit_latency_hist::gmean 1
-system.ruby.IFETCH.hit_latency_hist::stdev nan
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 1
+system.ruby.IFETCH.latency_hist::samples 63
+system.ruby.IFETCH.latency_hist::mean 107.476190
+system.ruby.IFETCH.latency_hist::gmean 95.146533
+system.ruby.IFETCH.latency_hist::stdev 52.448702
+system.ruby.IFETCH.latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 63
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
-system.ruby.IFETCH.miss_latency_hist::samples 56
-system.ruby.IFETCH.miss_latency_hist::mean 107.107143
-system.ruby.IFETCH.miss_latency_hist::gmean 91.066566
-system.ruby.IFETCH.miss_latency_hist::stdev 61.178926
-system.ruby.IFETCH.miss_latency_hist | 14 25.00% 25.00% | 22 39.29% 64.29% | 16 28.57% 92.86% | 2 3.57% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 56
-system.ruby.Directory_Controller.Fetch 868 0.00% 0.00%
-system.ruby.Directory_Controller.Data 777 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 777 0.00% 0.00%
+system.ruby.IFETCH.miss_latency_hist::samples 63
+system.ruby.IFETCH.miss_latency_hist::mean 107.476190
+system.ruby.IFETCH.miss_latency_hist::gmean 95.146533
+system.ruby.IFETCH.miss_latency_hist::stdev 52.448702
+system.ruby.IFETCH.miss_latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 63
+system.ruby.Directory_Controller.Fetch 902 0.00% 0.00%
+system.ruby.Directory_Controller.Data 811 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 902 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 811 0.00% 0.00%
system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 868 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 777 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 902 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 811 0.00% 0.00%
system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 868 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 777 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 43 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 875 0.00% 0.00%
-system.ruby.L1Cache_Controller.Inv 264 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 12024 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_all_Acks 866 0.00% 0.00%
-system.ruby.L1Cache_Controller.WB_Ack 782 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 56 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 812 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Inv 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement 112 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Inv 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.Inv 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement 39 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 63 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Inv 64 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 745 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 555 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks 49 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10564 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks 810 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch 8 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Inv 151 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack 631 0.00% 0.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 151 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GET_INSTR 56 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 810 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 632 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 902 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 811 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 37 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 67 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 927 0.00% 0.00%
+system.ruby.L1Cache_Controller.Inv 278 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 12331 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_Exclusive 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_all_Acks 906 0.00% 0.00%
+system.ruby.L1Cache_Controller.WB_Ack 808 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch 64 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Store 845 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement 121 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Inv 54 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.Inv 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement 25 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 7 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 82 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Inv 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 785 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Inv 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 386 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 11011 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks 843 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.Inv 156 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack 652 0.00% 0.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 156 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GET_INSTR 64 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 30 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 844 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 653 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX_old 267 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 574 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 530 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 868 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 203 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 49 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 850 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 780 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old 135 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 574 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 632 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 216 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 16 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 116 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 203 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 93 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 123 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 780 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 842 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 603 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 569 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 902 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 898 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 208 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 65 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 873 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 61 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 814 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old 134 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 603 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 18 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 653 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 219 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 22 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 898 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 111 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 208 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 121 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 125 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 813 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 20 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 870 0.00% 0.00%
---------- End Simulation Statistics ----------
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l1_cntrl0.triggerQueue]
type=MessageBuffer
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:46:21
-gem5 started Nov 15 2015 14:46:44
-gem5 executing on ribera.cs.wisc.edu, pid 1173
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
+gem5 compiled Dec 11 2015 20:10:49
+gem5 started Dec 11 2015 20:11:27
+gem5 executing on zizzer, pid 42474
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 53711 because Ruby Tester completed
+Exiting @ tick 54211 because Ruby Tester completed
---------- Begin Simulation Statistics ----------
sim_seconds 0.000054 # Number of seconds simulated
-sim_ticks 53711 # Number of ticks simulated
-final_tick 53711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 54211 # Number of ticks simulated
+final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 378504 # Simulator tick rate (ticks/s)
-host_mem_usage 447852 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 209714 # Simulator tick rate (ticks/s)
+host_mem_usage 387824 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54528 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 54528 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48448 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 48448 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 852 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 852 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 757 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 757 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1015211037 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1015211037 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 902012623 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 902012623 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917223660 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1917223660 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 852 # Number of read requests accepted
-system.mem_ctrls.writeReqs 757 # Number of write requests accepted
-system.mem_ctrls.readBursts 852 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 757 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 8896 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 54528 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 48448 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 94 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48256 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 48256 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 754 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 754 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 996402944 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 996402944 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 890151445 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 890151445 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1886554389 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1886554389 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 844 # Number of read requests accepted
+system.mem_ctrls.writeReqs 754 # Number of write requests accepted
+system.mem_ctrls.readBursts 844 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 754 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 7296 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 42112 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 54016 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 48256 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 77 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 212 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 227 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 250 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 190 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 199 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 208 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 219 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 42 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 53660 # Total gap between requests
+system.mem_ctrls.totGap 54170 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 852 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 844 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 757 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 567 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 143 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 754 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 587 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 140 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 21 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 37 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 36 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 36 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 889.191489 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 796.949082 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 278.173972 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 2 2.13% 2.13% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 4 4.26% 6.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 5 5.32% 11.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3 3.19% 14.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 1 1.06% 15.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 2 2.13% 18.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 20.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 5 5.32% 25.53% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 70 74.47% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 36 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 19.277778 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 18.954063 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 4.046947 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 3 8.33% 8.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 9 25.00% 33.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 11 30.56% 63.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 5 13.89% 77.78% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 6 16.67% 94.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-25 1 2.78% 97.22% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::38-39 1 2.78% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 36 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 36 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.555556 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.508645 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.297127 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13 36.11% 36.11% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 2.78% 38.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 12 33.33% 72.22% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 9 25.00% 97.22% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 1 2.78% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 36 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 5835 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 19382 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 8.18 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 97 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 888.742268 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 795.135498 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 283.200947 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 8 8.25% 8.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.06% 10.31% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 3 3.09% 13.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2 2.06% 15.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 4.12% 19.59% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1 1.03% 20.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 2 2.06% 22.68% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 75 77.32% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 97 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 19.052632 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 18.749953 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.938359 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 2 5.26% 5.26% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 13 34.21% 39.47% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 9 23.68% 63.16% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 8 21.05% 84.21% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 4 10.53% 94.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-25 1 2.63% 97.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::38-39 1 2.63% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17.315789 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 17.271887 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.254296 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 16 42.11% 42.11% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 2 5.26% 47.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 13 34.21% 81.58% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 6 15.79% 97.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 1 2.63% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 6080 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 19950 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 8.33 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 27.18 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 849.58 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 753.07 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1015.21 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 902.01 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 27.33 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 861.82 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 776.82 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 996.40 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 890.15 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 12.52 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 6.64 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 5.88 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.35 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.46 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 622 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 94.27 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 33.35 # Average gap between requests
-system.mem_ctrls.pageHitRate 90.62 # Row buffer hit rate, read and write combined
+system.mem_ctrls.busUtil 12.80 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 6.73 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 6.07 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.34 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 24.81 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 637 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 650 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.26 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 96.01 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 33.90 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.47 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 650160 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 361200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7700160 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5816448 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7725120 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 5723136 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 32013252 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 103800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 49696380 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1057.909997 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 49628028 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1056.454956 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 972
-system.ruby.outstanding_req_hist::mean 15.762346
-system.ruby.outstanding_req_hist::gmean 15.655254
-system.ruby.outstanding_req_hist::stdev 1.201656
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.65% | 94 9.67% 11.32% | 862 88.68% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 972
+system.ruby.outstanding_req_hist::samples 985
+system.ruby.outstanding_req_hist::mean 15.747208
+system.ruby.outstanding_req_hist::gmean 15.641156
+system.ruby.outstanding_req_hist::stdev 1.199617
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.41% 1.12% | 2 0.20% 1.32% | 3 0.30% 1.62% | 110 11.17% 12.79% | 859 87.21% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 985
system.ruby.latency_hist::bucket_size 256
system.ruby.latency_hist::max_bucket 2559
-system.ruby.latency_hist::samples 957
-system.ruby.latency_hist::mean 881.794148
-system.ruby.latency_hist::gmean 495.949804
-system.ruby.latency_hist::stdev 359.464211
-system.ruby.latency_hist | 135 14.11% 14.11% | 6 0.63% 14.73% | 4 0.42% 15.15% | 442 46.19% 61.34% | 349 36.47% 97.81% | 21 2.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 957
+system.ruby.latency_hist::samples 970
+system.ruby.latency_hist::mean 876.382474
+system.ruby.latency_hist::gmean 454.463576
+system.ruby.latency_hist::stdev 370.932806
+system.ruby.latency_hist | 146 15.05% 15.05% | 6 0.62% 15.67% | 4 0.41% 16.08% | 388 40.00% 56.08% | 418 43.09% 99.18% | 8 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 970
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 75
+system.ruby.hit_latency_hist::samples 92
system.ruby.hit_latency_hist::mean 1
system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 75
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 92
system.ruby.miss_latency_hist::bucket_size 256
system.ruby.miss_latency_hist::max_bucket 2559
-system.ruby.miss_latency_hist::samples 882
-system.ruby.miss_latency_hist::mean 956.691610
-system.ruby.miss_latency_hist::gmean 840.701090
-system.ruby.miss_latency_hist::stdev 261.829138
-system.ruby.miss_latency_hist | 60 6.80% 6.80% | 6 0.68% 7.48% | 4 0.45% 7.94% | 442 50.11% 58.05% | 349 39.57% 97.62% | 21 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 882
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 75 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 832 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 907 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 76 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 3 # Number of times a load aliased with a pending store
-system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 852 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 882 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 878
+system.ruby.miss_latency_hist::mean 968.108200
+system.ruby.miss_latency_hist::gmean 862.901849
+system.ruby.miss_latency_hist::stdev 251.425992
+system.ruby.miss_latency_hist | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 878
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 44 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 75 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 36 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 844 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 880 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 9.006070
-system.ruby.network.routers0.msg_count.Request_Control::0 882
-system.ruby.network.routers0.msg_count.Response_Data::2 852
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 30
-system.ruby.network.routers0.msg_count.Writeback_Data::2 877
-system.ruby.network.routers0.msg_count.Writeback_Control::0 1754
-system.ruby.network.routers0.msg_count.Unblock_Control::2 882
-system.ruby.network.routers0.msg_bytes.Request_Control::0 7056
-system.ruby.network.routers0.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2160
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2 63144
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14032
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7056
-system.ruby.network.routers1.percent_links_utilized 17.246933
-system.ruby.network.routers1.msg_count.Request_Control::0 882
-system.ruby.network.routers1.msg_count.Request_Control::1 852
-system.ruby.network.routers1.msg_count.Response_Data::2 1704
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 30
-system.ruby.network.routers1.msg_count.Writeback_Data::2 1635
-system.ruby.network.routers1.msg_count.Writeback_Control::0 1754
-system.ruby.network.routers1.msg_count.Writeback_Control::1 1516
-system.ruby.network.routers1.msg_count.Unblock_Control::2 1732
-system.ruby.network.routers1.msg_bytes.Request_Control::0 7056
-system.ruby.network.routers1.msg_bytes.Request_Control::1 6816
-system.ruby.network.routers1.msg_bytes.Response_Data::2 122688
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2160
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2 117720
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14032
-system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12128
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13856
-system.ruby.network.routers2.percent_links_utilized 8.238536
-system.ruby.network.routers2.msg_count.Request_Control::1 852
-system.ruby.network.routers2.msg_count.Response_Data::2 852
-system.ruby.network.routers2.msg_count.Writeback_Data::2 757
-system.ruby.network.routers2.msg_count.Writeback_Control::1 1516
-system.ruby.network.routers2.msg_count.Unblock_Control::2 851
-system.ruby.network.routers2.msg_bytes.Request_Control::1 6816
-system.ruby.network.routers2.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers2.msg_bytes.Writeback_Data::2 54504
-system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12128
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6808
-system.ruby.network.routers3.percent_links_utilized 11.497024
-system.ruby.network.routers3.msg_count.Request_Control::0 882
-system.ruby.network.routers3.msg_count.Request_Control::1 852
-system.ruby.network.routers3.msg_count.Response_Data::2 1704
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 30
-system.ruby.network.routers3.msg_count.Writeback_Data::2 1635
-system.ruby.network.routers3.msg_count.Writeback_Control::0 1754
-system.ruby.network.routers3.msg_count.Writeback_Control::1 1516
-system.ruby.network.routers3.msg_count.Unblock_Control::2 1733
-system.ruby.network.routers3.msg_bytes.Request_Control::0 7056
-system.ruby.network.routers3.msg_bytes.Request_Control::1 6816
-system.ruby.network.routers3.msg_bytes.Response_Data::2 122688
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2160
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2 117720
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14032
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12128
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13864
-system.ruby.network.msg_count.Request_Control 5202
-system.ruby.network.msg_count.Response_Data 5112
-system.ruby.network.msg_count.ResponseL2hit_Data 90
-system.ruby.network.msg_count.Writeback_Data 4904
-system.ruby.network.msg_count.Writeback_Control 9810
-system.ruby.network.msg_count.Unblock_Control 5198
-system.ruby.network.msg_byte.Request_Control 41616
-system.ruby.network.msg_byte.Response_Data 368064
-system.ruby.network.msg_byte.ResponseL2hit_Data 6480
-system.ruby.network.msg_byte.Writeback_Data 353088
-system.ruby.network.msg_byte.Writeback_Control 78480
-system.ruby.network.msg_byte.Unblock_Control 41584
-system.ruby.network.routers0.throttle0.link_utilization 8.205954
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 852
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 30
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 877
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2160
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7016
-system.ruby.network.routers0.throttle1.link_utilization 9.806185
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 882
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 877
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 877
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 882
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7056
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 63144
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7016
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7056
-system.ruby.network.routers1.throttle0.link_utilization 17.649085
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 882
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 852
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 877
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 877
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 758
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 881
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7056
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 63144
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7016
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6064
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7048
-system.ruby.network.routers1.throttle1.link_utilization 16.844780
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 852
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 852
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 30
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 758
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 877
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 758
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 851
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6816
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2160
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 54576
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7016
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6064
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6808
-system.ruby.network.routers2.throttle0.link_utilization 8.633241
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 852
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 757
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 758
-system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 851
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6816
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 54504
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6064
-system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6808
-system.ruby.network.routers2.throttle1.link_utilization 7.843831
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 852
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 758
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6064
-system.ruby.network.routers3.throttle0.link_utilization 8.205954
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 852
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 30
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 877
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2160
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7016
-system.ruby.network.routers3.throttle1.link_utilization 17.650016
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 882
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 852
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 877
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 877
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 758
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 882
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7056
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 61344
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 63144
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7016
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6064
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7056
-system.ruby.network.routers3.throttle2.link_utilization 8.635103
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 852
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 758
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 758
-system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 851
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6816
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 54576
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6064
-system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6808
-system.ruby.LD.latency_hist::bucket_size 256
-system.ruby.LD.latency_hist::max_bucket 2559
-system.ruby.LD.latency_hist::samples 50
-system.ruby.LD.latency_hist::mean 914.500000
-system.ruby.LD.latency_hist::gmean 544.079764
-system.ruby.LD.latency_hist::stdev 318.769653
-system.ruby.LD.latency_hist | 5 10.00% 10.00% | 0 0.00% 10.00% | 0 0.00% 10.00% | 30 60.00% 70.00% | 13 26.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 50
+system.ruby.network.routers0.percent_links_utilized 8.888879
+system.ruby.network.routers0.msg_count.Request_Control::0 880
+system.ruby.network.routers0.msg_count.Response_Data::2 843
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 35
+system.ruby.network.routers0.msg_count.Writeback_Data::2 874
+system.ruby.network.routers0.msg_count.Writeback_Control::0 1749
+system.ruby.network.routers0.msg_count.Unblock_Control::2 878
+system.ruby.network.routers0.msg_bytes.Request_Control::0 7040
+system.ruby.network.routers0.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2520
+system.ruby.network.routers0.msg_bytes.Writeback_Data::2 62928
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 13992
+system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7024
+system.ruby.network.routers1.percent_links_utilized 16.994245
+system.ruby.network.routers1.msg_count.Request_Control::0 880
+system.ruby.network.routers1.msg_count.Request_Control::1 844
+system.ruby.network.routers1.msg_count.Response_Data::2 1686
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 36
+system.ruby.network.routers1.msg_count.Writeback_Data::2 1628
+system.ruby.network.routers1.msg_count.Writeback_Control::0 1749
+system.ruby.network.routers1.msg_count.Writeback_Control::1 1509
+system.ruby.network.routers1.msg_count.Unblock_Control::2 1720
+system.ruby.network.routers1.msg_bytes.Request_Control::0 7040
+system.ruby.network.routers1.msg_bytes.Request_Control::1 6752
+system.ruby.network.routers1.msg_bytes.Response_Data::2 121392
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2592
+system.ruby.network.routers1.msg_bytes.Writeback_Data::2 117216
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 13992
+system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12072
+system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13760
+system.ruby.network.routers2.percent_links_utilized 8.101677
+system.ruby.network.routers2.msg_count.Request_Control::1 844
+system.ruby.network.routers2.msg_count.Response_Data::2 843
+system.ruby.network.routers2.msg_count.Writeback_Data::2 754
+system.ruby.network.routers2.msg_count.Writeback_Control::1 1509
+system.ruby.network.routers2.msg_count.Unblock_Control::2 842
+system.ruby.network.routers2.msg_bytes.Request_Control::1 6752
+system.ruby.network.routers2.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers2.msg_bytes.Writeback_Data::2 54288
+system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12072
+system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6736
+system.ruby.network.routers3.percent_links_utilized 11.328267
+system.ruby.network.routers3.msg_count.Request_Control::0 880
+system.ruby.network.routers3.msg_count.Request_Control::1 844
+system.ruby.network.routers3.msg_count.Response_Data::2 1686
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 36
+system.ruby.network.routers3.msg_count.Writeback_Data::2 1628
+system.ruby.network.routers3.msg_count.Writeback_Control::0 1749
+system.ruby.network.routers3.msg_count.Writeback_Control::1 1509
+system.ruby.network.routers3.msg_count.Unblock_Control::2 1720
+system.ruby.network.routers3.msg_bytes.Request_Control::0 7040
+system.ruby.network.routers3.msg_bytes.Request_Control::1 6752
+system.ruby.network.routers3.msg_bytes.Response_Data::2 121392
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2592
+system.ruby.network.routers3.msg_bytes.Writeback_Data::2 117216
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 13992
+system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12072
+system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13760
+system.ruby.network.msg_count.Request_Control 5172
+system.ruby.network.msg_count.Response_Data 5058
+system.ruby.network.msg_count.ResponseL2hit_Data 107
+system.ruby.network.msg_count.Writeback_Data 4884
+system.ruby.network.msg_count.Writeback_Control 9774
+system.ruby.network.msg_count.Unblock_Control 5160
+system.ruby.network.msg_byte.Request_Control 41376
+system.ruby.network.msg_byte.Response_Data 364176
+system.ruby.network.msg_byte.ResponseL2hit_Data 7704
+system.ruby.network.msg_byte.Writeback_Data 351648
+system.ruby.network.msg_byte.Writeback_Control 78192
+system.ruby.network.msg_byte.Unblock_Control 41280
+system.ruby.network.routers0.throttle0.link_utilization 8.094298
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 843
+system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 35
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 874
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2520
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 6992
+system.ruby.network.routers0.throttle1.link_utilization 9.683459
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 880
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 874
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 875
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 878
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7040
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 62928
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7000
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7024
+system.ruby.network.routers1.throttle0.link_utilization 17.376547
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 880
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 843
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 874
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 875
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 754
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 878
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7040
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 62928
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7000
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6032
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7024
+system.ruby.network.routers1.throttle1.link_utilization 16.611942
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 844
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 843
+system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 36
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 754
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 874
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 755
+system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 842
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6752
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2592
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 54288
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 6992
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6040
+system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6736
+system.ruby.network.routers2.throttle0.link_utilization 8.510265
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 844
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 754
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 755
+system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 842
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6752
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 54288
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6040
+system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6736
+system.ruby.network.routers2.throttle1.link_utilization 7.693088
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 843
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 754
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6032
+system.ruby.network.routers3.throttle0.link_utilization 8.097987
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 843
+system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 36
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 874
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2592
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 6992
+system.ruby.network.routers3.throttle1.link_utilization 17.376547
+system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 880
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 843
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 874
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 875
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 754
+system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 878
+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7040
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 60696
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 62928
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7000
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6032
+system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7024
+system.ruby.network.routers3.throttle2.link_utilization 8.510265
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 844
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 754
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 755
+system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 842
+system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6752
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 54288
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6040
+system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6736
+system.ruby.LD.latency_hist::bucket_size 128
+system.ruby.LD.latency_hist::max_bucket 1279
+system.ruby.LD.latency_hist::samples 54
+system.ruby.LD.latency_hist::mean 874.574074
+system.ruby.LD.latency_hist::gmean 437.265598
+system.ruby.LD.latency_hist::stdev 350.325488
+system.ruby.LD.latency_hist | 7 12.96% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 5 9.26% 22.22% | 29 53.70% 75.93% | 9 16.67% 92.59% | 4 7.41% 100.00%
+system.ruby.LD.latency_hist::total 54
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
-system.ruby.LD.hit_latency_hist::samples 4
+system.ruby.LD.hit_latency_hist::samples 6
system.ruby.LD.hit_latency_hist::mean 1
system.ruby.LD.hit_latency_hist::gmean 1
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 4
-system.ruby.LD.miss_latency_hist::bucket_size 256
-system.ruby.LD.miss_latency_hist::max_bucket 2559
-system.ruby.LD.miss_latency_hist::samples 46
-system.ruby.LD.miss_latency_hist::mean 993.934783
-system.ruby.LD.miss_latency_hist::gmean 940.906082
-system.ruby.LD.miss_latency_hist::stdev 173.263243
-system.ruby.LD.miss_latency_hist | 1 2.17% 2.17% | 0 0.00% 2.17% | 0 0.00% 2.17% | 30 65.22% 67.39% | 13 28.26% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 46
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 6
+system.ruby.LD.miss_latency_hist::bucket_size 128
+system.ruby.LD.miss_latency_hist::max_bucket 1279
+system.ruby.LD.miss_latency_hist::samples 48
+system.ruby.LD.miss_latency_hist::mean 983.770833
+system.ruby.LD.miss_latency_hist::gmean 935.057837
+system.ruby.LD.miss_latency_hist::stdev 169.695753
+system.ruby.LD.miss_latency_hist | 1 2.08% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 5 10.42% 12.50% | 29 60.42% 72.92% | 9 18.75% 91.67% | 4 8.33% 100.00%
+system.ruby.LD.miss_latency_hist::total 48
system.ruby.ST.latency_hist::bucket_size 256
system.ruby.ST.latency_hist::max_bucket 2559
-system.ruby.ST.latency_hist::samples 857
-system.ruby.ST.latency_hist::mean 927.439907
-system.ruby.ST.latency_hist::gmean 556.916459
-system.ruby.ST.latency_hist::stdev 312.242258
-system.ruby.ST.latency_hist | 80 9.33% 9.33% | 6 0.70% 10.04% | 4 0.47% 10.50% | 412 48.07% 58.58% | 336 39.21% 97.78% | 19 2.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 857
+system.ruby.ST.latency_hist::samples 870
+system.ruby.ST.latency_hist::mean 919.120690
+system.ruby.ST.latency_hist::gmean 509.527867
+system.ruby.ST.latency_hist::stdev 331.108106
+system.ruby.ST.latency_hist | 93 10.69% 10.69% | 6 0.69% 11.38% | 4 0.46% 11.84% | 354 40.69% 52.53% | 405 46.55% 99.08% | 8 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 870
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
-system.ruby.ST.hit_latency_hist::samples 71
+system.ruby.ST.hit_latency_hist::samples 84
system.ruby.ST.hit_latency_hist::mean 1
system.ruby.ST.hit_latency_hist::gmean 1
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 71 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 71
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 84
system.ruby.ST.miss_latency_hist::bucket_size 256
system.ruby.ST.miss_latency_hist::max_bucket 2559
system.ruby.ST.miss_latency_hist::samples 786
-system.ruby.ST.miss_latency_hist::mean 1011.125954
-system.ruby.ST.miss_latency_hist::gmean 985.869507
-system.ruby.ST.miss_latency_hist::stdev 147.214582
-system.ruby.ST.miss_latency_hist | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 412 52.42% 54.83% | 336 42.75% 97.58% | 19 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::mean 1017.240458
+system.ruby.ST.miss_latency_hist::gmean 991.935880
+system.ruby.ST.miss_latency_hist::stdev 146.709443
+system.ruby.ST.miss_latency_hist | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 354 45.04% 47.46% | 405 51.53% 98.98% | 8 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist::total 786
system.ruby.IFETCH.latency_hist::bucket_size 32
system.ruby.IFETCH.latency_hist::max_bucket 319
-system.ruby.IFETCH.latency_hist::samples 50
-system.ruby.IFETCH.latency_hist::mean 66.720000
-system.ruby.IFETCH.latency_hist::gmean 61.968921
-system.ruby.IFETCH.latency_hist::stdev 27.740812
-system.ruby.IFETCH.latency_hist | 1 2.00% 2.00% | 19 38.00% 40.00% | 28 56.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 50
+system.ruby.IFETCH.latency_hist::samples 46
+system.ruby.IFETCH.latency_hist::mean 70.195652
+system.ruby.IFETCH.latency_hist::gmean 54.673545
+system.ruby.IFETCH.latency_hist::stdev 37.753363
+system.ruby.IFETCH.latency_hist | 4 8.70% 8.70% | 14 30.43% 39.13% | 21 45.65% 84.78% | 1 2.17% 86.96% | 4 8.70% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 46
+system.ruby.IFETCH.hit_latency_hist::bucket_size 1
+system.ruby.IFETCH.hit_latency_hist::max_bucket 9
+system.ruby.IFETCH.hit_latency_hist::samples 2
+system.ruby.IFETCH.hit_latency_hist::mean 1
+system.ruby.IFETCH.hit_latency_hist::gmean 1
+system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 2
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
-system.ruby.IFETCH.miss_latency_hist::samples 50
-system.ruby.IFETCH.miss_latency_hist::mean 66.720000
-system.ruby.IFETCH.miss_latency_hist::gmean 61.968921
-system.ruby.IFETCH.miss_latency_hist::stdev 27.740812
-system.ruby.IFETCH.miss_latency_hist | 1 2.00% 2.00% | 19 38.00% 40.00% | 28 56.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 50
-system.ruby.Directory_Controller.GETX 763 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 89 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 758 0.00% 0.00%
-system.ruby.Directory_Controller.Unblock 84 0.00% 0.00%
-system.ruby.Directory_Controller.Last_Unblock 4 0.00% 0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock 763 0.00% 0.00%
-system.ruby.Directory_Controller.Dirty_Writeback 757 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 852 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 757 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 700 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETS 85 0.00% 0.00%
-system.ruby.Directory_Controller.I.Memory_Ack 757 0.00% 0.00%
-system.ruby.Directory_Controller.S.GETX 63 0.00% 0.00%
-system.ruby.Directory_Controller.S.GETS 4 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 758 0.00% 0.00%
-system.ruby.Directory_Controller.IS.Unblock 84 0.00% 0.00%
-system.ruby.Directory_Controller.IS.Memory_Data 85 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock 4 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Memory_Data 4 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock 763 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Memory_Data 763 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback 757 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 52 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 60 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 79286 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 89 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 793 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data 877 0.00% 0.00%
+system.ruby.IFETCH.miss_latency_hist::samples 44
+system.ruby.IFETCH.miss_latency_hist::mean 73.340909
+system.ruby.IFETCH.miss_latency_hist::gmean 65.579350
+system.ruby.IFETCH.miss_latency_hist::stdev 35.479403
+system.ruby.IFETCH.miss_latency_hist | 2 4.55% 4.55% | 14 31.82% 36.36% | 21 47.73% 84.09% | 1 2.27% 86.36% | 4 9.09% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 44
+system.ruby.Directory_Controller.GETX 761 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 83 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 755 0.00% 0.00%
+system.ruby.Directory_Controller.Unblock 77 0.00% 0.00%
+system.ruby.Directory_Controller.Last_Unblock 5 0.00% 0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.Directory_Controller.Dirty_Writeback 754 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 843 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 754 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 691 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00%
+system.ruby.Directory_Controller.I.Memory_Ack 754 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETX 70 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETS 5 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 755 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock 5 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Memory_Data 5 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Memory_Data 760 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback 754 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 56 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 59 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 880 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 80012 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 83 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 874 0.00% 0.00%
system.ruby.L1Cache_Controller.All_acks 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_Timeout 792 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 87 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_Timeout 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 48 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 44 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 788 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 81 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 59 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 784 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31474 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout 785 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 44509 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 7 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 68 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 787 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Load 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 15 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30902 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout 786 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 45597 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Exclusive_Data 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement 45 0.00% 0.00%
system.ruby.L1Cache_Controller.OM.All_acks 786 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 2365 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 89 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 87 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 2588 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 83 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 81 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Ifetch 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Ifetch 13 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Store 8 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 96 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 786 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 852 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 758 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 88 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 793 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 844 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 89 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 86 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 23 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 758 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 87 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 790 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 89 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 88 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 763 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 23 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 758 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 92 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 788 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 794 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 843 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 754 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 795 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 836 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 761 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 794 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 755 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 26 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 754 0.00% 0.00%
---------- End Simulation Statistics ----------
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:51:28
-gem5 started Nov 15 2015 14:51:52
-gem5 executing on ribera.cs.wisc.edu, pid 2888
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
+gem5 compiled Dec 11 2015 20:15:50
+gem5 started Dec 11 2015 20:16:20
+gem5 executing on zizzer, pid 47648
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 53241 because Ruby Tester completed
+Exiting @ tick 50141 because Ruby Tester completed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000053 # Number of seconds simulated
-sim_ticks 53241 # Number of ticks simulated
-final_tick 53241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000050 # Number of seconds simulated
+sim_ticks 50141 # Number of ticks simulated
+final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 626475 # Simulator tick rate (ticks/s)
-host_mem_usage 446792 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 455774 # Simulator tick rate (ticks/s)
+host_mem_usage 387088 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49216 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49216 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 769 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 769 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1014556451 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1014556451 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 924400368 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 924400368 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1938956819 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1938956819 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 845 # Number of read requests accepted
-system.mem_ctrls.writeReqs 769 # Number of write requests accepted
-system.mem_ctrls.readBursts 845 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 769 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9280 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 41856 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 54080 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49216 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 145 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 91 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 50624 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 46016 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 46016 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 791 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 791 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 719 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 719 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1009632835 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1009632835 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 917731996 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 917731996 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1927364831 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1927364831 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 791 # Number of read requests accepted
+system.mem_ctrls.writeReqs 719 # Number of write requests accepted
+system.mem_ctrls.readBursts 791 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 719 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 42944 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 7680 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 39296 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 50624 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 46016 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 211 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 216 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 208 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 221 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 189 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 195 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 213 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 43 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 195 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 180 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 50 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 53206 # Total gap between requests
+system.mem_ctrls.totGap 50084 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 845 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 791 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 769 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 596 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 104 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 719 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 557 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 111 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 20 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 926.241758 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 851.755825 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 236.278712 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 2 2.20% 2.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 3 3.30% 5.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 1 1.10% 6.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 3 3.30% 9.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3 3.30% 13.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 4.40% 17.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3 3.30% 20.88% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 72 79.12% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.325000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.063768 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.661214 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 9 22.50% 22.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 70.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 8 20.00% 90.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 95.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 2.50% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.350000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.325620 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 34 85.00% 85.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 2 5.00% 90.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 2 5.00% 97.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 1 2.50% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 7789 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 21089 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 11.13 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 910.382022 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 810.808230 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 274.216052 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 2 2.25% 2.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 5 5.62% 7.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.25% 10.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 1 1.12% 11.24% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 1 1.12% 12.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 2 2.25% 14.61% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1 1.12% 15.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 3.37% 19.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 72 80.90% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 17.394737 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.106045 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.831163 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 8 21.05% 21.05% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 18 47.37% 68.42% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 7 18.42% 86.84% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 3 7.89% 94.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 1 2.63% 97.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-37 1 2.63% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.157895 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.145372 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.678883 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 36 94.74% 94.74% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 8848 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 21597 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3355 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 13.19 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 30.13 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 841.46 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 786.16 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1015.76 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 924.40 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 32.19 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 856.46 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 783.71 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1009.63 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 917.73 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 12.72 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 6.57 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 6.14 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.08 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 611 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 649 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.29 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.72 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 32.97 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.44 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 627480 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 348600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7712640 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5920128 # Energy for write commands per rank (pJ)
+system.mem_ctrls.busUtil 12.81 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 6.69 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 6.12 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.30 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 25.17 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 582 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 610 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 86.74 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 95.61 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 33.17 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.06 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7775040 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6003072 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 32011200 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 105600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 49777008 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1059.626362 # Core power per rank (mW)
+system.mem_ctrls_0.actBackEnergy 32001624 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 114000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 49944696 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1063.196015 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 1000
-system.ruby.outstanding_req_hist::mean 15.805000
-system.ruby.outstanding_req_hist::gmean 15.701069
-system.ruby.outstanding_req_hist::stdev 1.178288
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.10% | 2 0.20% 1.30% | 3 0.30% 1.60% | 58 5.80% 7.40% | 926 92.60% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 1000
+system.ruby.outstanding_req_hist::samples 961
+system.ruby.outstanding_req_hist::mean 15.762747
+system.ruby.outstanding_req_hist::gmean 15.654325
+system.ruby.outstanding_req_hist::stdev 1.209298
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.42% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.47% 11.13% | 854 88.87% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 961
system.ruby.latency_hist::bucket_size 256
system.ruby.latency_hist::max_bucket 2559
-system.ruby.latency_hist::samples 985
-system.ruby.latency_hist::mean 848.757360
-system.ruby.latency_hist::gmean 399.302244
-system.ruby.latency_hist::stdev 414.190992
-system.ruby.latency_hist | 190 19.29% 19.29% | 6 0.61% 19.90% | 5 0.51% 20.41% | 342 34.72% 55.13% | 403 40.91% 96.04% | 39 3.96% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 985
+system.ruby.latency_hist::samples 946
+system.ruby.latency_hist::mean 831.747357
+system.ruby.latency_hist::gmean 353.331206
+system.ruby.latency_hist::stdev 440.661399
+system.ruby.latency_hist | 208 21.99% 21.99% | 7 0.74% 22.73% | 5 0.53% 23.26% | 262 27.70% 50.95% | 409 43.23% 94.19% | 55 5.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 946
system.ruby.hit_latency_hist::bucket_size 256
system.ruby.hit_latency_hist::max_bucket 2559
-system.ruby.hit_latency_hist::samples 141
-system.ruby.hit_latency_hist::mean 184.574468
-system.ruby.hit_latency_hist::gmean 5.430666
-system.ruby.hit_latency_hist::stdev 386.473899
-system.ruby.hit_latency_hist | 116 82.27% 82.27% | 0 0.00% 82.27% | 0 0.00% 82.27% | 19 13.48% 95.74% | 4 2.84% 98.58% | 2 1.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 141
+system.ruby.hit_latency_hist::samples 156
+system.ruby.hit_latency_hist::mean 161.115385
+system.ruby.hit_latency_hist::gmean 5.208817
+system.ruby.hit_latency_hist::stdev 361.858143
+system.ruby.hit_latency_hist | 132 84.62% 84.62% | 0 0.00% 84.62% | 0 0.00% 84.62% | 17 10.90% 95.51% | 6 3.85% 99.36% | 1 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 156
system.ruby.miss_latency_hist::bucket_size 256
system.ruby.miss_latency_hist::max_bucket 2559
-system.ruby.miss_latency_hist::samples 844
-system.ruby.miss_latency_hist::mean 959.716825
-system.ruby.miss_latency_hist::gmean 818.679034
-system.ruby.miss_latency_hist::stdev 298.884250
-system.ruby.miss_latency_hist | 74 8.77% 8.77% | 6 0.71% 9.48% | 5 0.59% 10.07% | 323 38.27% 48.34% | 399 47.27% 95.62% | 37 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 844
-system.ruby.Directory.incomplete_times 844
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 97 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 841 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 938 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 790
+system.ruby.miss_latency_hist::mean 964.175949
+system.ruby.miss_latency_hist::gmean 812.519909
+system.ruby.miss_latency_hist::stdev 316.811320
+system.ruby.miss_latency_hist | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 790
+system.ruby.Directory.incomplete_times 790
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 105 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 788 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 893 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 47 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
-system.ruby.l2_cntrl0.L2cache.demand_hits 42 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 888 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 55 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 74 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 48 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 793 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 841 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 8.048309
-system.ruby.network.routers0.msg_count.Request_Control::1 888
-system.ruby.network.routers0.msg_count.Response_Data::4 844
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 43
+system.ruby.network.routers0.percent_links_utilized 8.090684
+system.ruby.network.routers0.msg_count.Request_Control::1 841
+system.ruby.network.routers0.msg_count.Response_Data::4 790
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 50
system.ruby.network.routers0.msg_count.Response_Control::4 1
-system.ruby.network.routers0.msg_count.Writeback_Data::4 912
-system.ruby.network.routers0.msg_count.Persistent_Control::3 60
-system.ruby.network.routers0.msg_bytes.Request_Control::1 7104
-system.ruby.network.routers0.msg_bytes.Response_Data::4 60768
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3096
+system.ruby.network.routers0.msg_count.Writeback_Data::4 862
+system.ruby.network.routers0.msg_count.Persistent_Control::3 68
+system.ruby.network.routers0.msg_bytes.Request_Control::1 6728
+system.ruby.network.routers0.msg_bytes.Response_Data::4 56880
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3600
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4 65664
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3 480
-system.ruby.network.routers1.percent_links_utilized 8.019665
-system.ruby.network.routers1.msg_count.Request_Control::1 888
-system.ruby.network.routers1.msg_count.Request_Control::2 846
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 43
+system.ruby.network.routers0.msg_bytes.Writeback_Data::4 62064
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3 544
+system.ruby.network.routers1.percent_links_utilized 8.057777
+system.ruby.network.routers1.msg_count.Request_Control::1 841
+system.ruby.network.routers1.msg_count.Request_Control::2 793
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 50
system.ruby.network.routers1.msg_count.Response_Control::4 1
-system.ruby.network.routers1.msg_count.Writeback_Data::4 1651
-system.ruby.network.routers1.msg_count.Writeback_Control::4 68
-system.ruby.network.routers1.msg_count.Persistent_Control::3 30
-system.ruby.network.routers1.msg_bytes.Request_Control::1 7104
-system.ruby.network.routers1.msg_bytes.Request_Control::2 6768
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3096
+system.ruby.network.routers1.msg_count.Writeback_Data::4 1553
+system.ruby.network.routers1.msg_count.Writeback_Control::4 65
+system.ruby.network.routers1.msg_count.Persistent_Control::3 34
+system.ruby.network.routers1.msg_bytes.Request_Control::1 6728
+system.ruby.network.routers1.msg_bytes.Request_Control::2 6344
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3600
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4 118872
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4 544
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers2.percent_links_utilized 7.259912
-system.ruby.network.routers2.msg_count.Request_Control::2 846
-system.ruby.network.routers2.msg_count.Response_Data::4 844
-system.ruby.network.routers2.msg_count.Writeback_Data::4 769
-system.ruby.network.routers2.msg_count.Writeback_Control::4 68
-system.ruby.network.routers2.msg_count.Persistent_Control::3 30
-system.ruby.network.routers2.msg_bytes.Request_Control::2 6768
-system.ruby.network.routers2.msg_bytes.Response_Data::4 60768
-system.ruby.network.routers2.msg_bytes.Writeback_Data::4 55368
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4 544
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers3.percent_links_utilized 7.775962
-system.ruby.network.routers3.msg_count.Request_Control::1 888
-system.ruby.network.routers3.msg_count.Request_Control::2 846
-system.ruby.network.routers3.msg_count.Response_Data::4 844
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 43
+system.ruby.network.routers1.msg_bytes.Writeback_Data::4 111816
+system.ruby.network.routers1.msg_bytes.Writeback_Control::4 520
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers2.percent_links_utilized 7.216150
+system.ruby.network.routers2.msg_count.Request_Control::2 793
+system.ruby.network.routers2.msg_count.Response_Data::4 790
+system.ruby.network.routers2.msg_count.Writeback_Data::4 719
+system.ruby.network.routers2.msg_count.Writeback_Control::4 65
+system.ruby.network.routers2.msg_count.Persistent_Control::3 34
+system.ruby.network.routers2.msg_bytes.Request_Control::2 6344
+system.ruby.network.routers2.msg_bytes.Response_Data::4 56880
+system.ruby.network.routers2.msg_bytes.Writeback_Data::4 51768
+system.ruby.network.routers2.msg_bytes.Writeback_Control::4 520
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers3.percent_links_utilized 7.788370
+system.ruby.network.routers3.msg_count.Request_Control::1 841
+system.ruby.network.routers3.msg_count.Request_Control::2 793
+system.ruby.network.routers3.msg_count.Response_Data::4 790
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 50
system.ruby.network.routers3.msg_count.Response_Control::4 1
-system.ruby.network.routers3.msg_count.Writeback_Data::4 1666
-system.ruby.network.routers3.msg_count.Writeback_Control::4 68
-system.ruby.network.routers3.msg_count.Persistent_Control::3 60
-system.ruby.network.routers3.msg_bytes.Request_Control::1 7104
-system.ruby.network.routers3.msg_bytes.Request_Control::2 6768
-system.ruby.network.routers3.msg_bytes.Response_Data::4 60768
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 3096
+system.ruby.network.routers3.msg_count.Writeback_Data::4 1567
+system.ruby.network.routers3.msg_count.Writeback_Control::4 65
+system.ruby.network.routers3.msg_count.Persistent_Control::3 68
+system.ruby.network.routers3.msg_bytes.Request_Control::1 6728
+system.ruby.network.routers3.msg_bytes.Request_Control::2 6344
+system.ruby.network.routers3.msg_bytes.Response_Data::4 56880
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 3600
system.ruby.network.routers3.msg_bytes.Response_Control::4 8
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4 119952
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4 544
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3 480
-system.ruby.network.msg_count.Request_Control 5202
-system.ruby.network.msg_count.Response_Data 2532
-system.ruby.network.msg_count.ResponseL2hit_Data 129
+system.ruby.network.routers3.msg_bytes.Writeback_Data::4 112824
+system.ruby.network.routers3.msg_bytes.Writeback_Control::4 520
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3 544
+system.ruby.network.msg_count.Request_Control 4902
+system.ruby.network.msg_count.Response_Data 2370
+system.ruby.network.msg_count.ResponseL2hit_Data 150
system.ruby.network.msg_count.Response_Control 3
-system.ruby.network.msg_count.Writeback_Data 4998
-system.ruby.network.msg_count.Writeback_Control 204
-system.ruby.network.msg_count.Persistent_Control 180
-system.ruby.network.msg_byte.Request_Control 41616
-system.ruby.network.msg_byte.Response_Data 182304
-system.ruby.network.msg_byte.ResponseL2hit_Data 9288
+system.ruby.network.msg_count.Writeback_Data 4701
+system.ruby.network.msg_count.Writeback_Control 195
+system.ruby.network.msg_count.Persistent_Control 204
+system.ruby.network.msg_byte.Request_Control 39216
+system.ruby.network.msg_byte.Response_Data 170640
+system.ruby.network.msg_byte.ResponseL2hit_Data 10800
system.ruby.network.msg_byte.Response_Control 24
-system.ruby.network.msg_byte.Writeback_Data 359856
-system.ruby.network.msg_byte.Writeback_Control 1632
-system.ruby.network.msg_byte.Persistent_Control 1440
-system.ruby.network.routers0.throttle0.link_utilization 7.652937
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 844
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 43
+system.ruby.network.msg_byte.Writeback_Data 338472
+system.ruby.network.msg_byte.Writeback_Control 1560
+system.ruby.network.msg_byte.Persistent_Control 1632
+system.ruby.network.routers0.throttle0.link_utilization 7.698291
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 790
+system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 50
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 15
-system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 30
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 60768
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 3096
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 14
+system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 34
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 56880
+system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 3600
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 1080
-system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers0.throttle1.link_utilization 8.443681
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 888
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 897
-system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 30
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 7104
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 64584
-system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers1.throttle0.link_utilization 8.316899
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 888
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 882
-system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 30
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 7104
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 63504
-system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers1.throttle1.link_utilization 7.722432
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 846
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 43
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 1008
+system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers0.throttle1.link_utilization 8.483078
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 841
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 848
+system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 34
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 6728
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 61056
+system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers1.throttle0.link_utilization 8.357432
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 841
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 834
+system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 34
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 6728
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 60048
+system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers1.throttle1.link_utilization 7.758122
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 793
+system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 50
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 769
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 68
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6768
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3096
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 719
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 65
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6344
+system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3600
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 55368
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 544
-system.ruby.network.routers2.throttle0.link_utilization 7.386225
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 846
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 769
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 68
-system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 30
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6768
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 55368
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 544
-system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers2.throttle1.link_utilization 7.133600
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 844
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 60768
-system.ruby.network.routers3.throttle0.link_utilization 7.624763
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 844
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 43
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 51768
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 520
+system.ruby.network.routers2.throttle0.link_utilization 7.342295
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 793
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 719
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 65
+system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 34
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6344
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 51768
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 520
+system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers2.throttle1.link_utilization 7.090006
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 790
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 56880
+system.ruby.network.routers3.throttle0.link_utilization 7.665384
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 790
+system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 50
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 15
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 60768
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 3096
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 14
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 56880
+system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 3600
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 1080
-system.ruby.network.routers3.throttle1.link_utilization 8.316899
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 888
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 882
-system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 30
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 7104
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 63504
-system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 240
-system.ruby.network.routers3.throttle2.link_utilization 7.386225
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 846
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 769
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 68
-system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 30
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6768
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 55368
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 544
-system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 240
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 1008
+system.ruby.network.routers3.throttle1.link_utilization 8.357432
+system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 841
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 834
+system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 34
+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 6728
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 60048
+system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers3.throttle2.link_utilization 7.342295
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 793
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 719
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 65
+system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 34
+system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6344
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 51768
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 520
+system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 272
system.ruby.LD.latency_hist::bucket_size 256
system.ruby.LD.latency_hist::max_bucket 2559
-system.ruby.LD.latency_hist::samples 52
-system.ruby.LD.latency_hist::mean 846.192308
-system.ruby.LD.latency_hist::gmean 310.504022
-system.ruby.LD.latency_hist::stdev 441.024789
-system.ruby.LD.latency_hist | 11 21.15% 21.15% | 0 0.00% 21.15% | 0 0.00% 21.15% | 14 26.92% 48.08% | 26 50.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 52
+system.ruby.LD.latency_hist::samples 46
+system.ruby.LD.latency_hist::mean 817.543478
+system.ruby.LD.latency_hist::gmean 284.544942
+system.ruby.LD.latency_hist::stdev 462.655942
+system.ruby.LD.latency_hist | 11 23.91% 23.91% | 0 0.00% 23.91% | 0 0.00% 23.91% | 15 32.61% 56.52% | 16 34.78% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist::total 46
system.ruby.LD.hit_latency_hist::bucket_size 128
system.ruby.LD.hit_latency_hist::max_bucket 1279
-system.ruby.LD.hit_latency_hist::samples 11
-system.ruby.LD.hit_latency_hist::mean 90.636364
-system.ruby.LD.hit_latency_hist::gmean 3.663774
-system.ruby.LD.hit_latency_hist::stdev 267.870220
-system.ruby.LD.hit_latency_hist | 10 90.91% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 11
+system.ruby.LD.hit_latency_hist::samples 10
+system.ruby.LD.hit_latency_hist::mean 101
+system.ruby.LD.hit_latency_hist::gmean 3.750098
+system.ruby.LD.hit_latency_hist::stdev 300.217329
+system.ruby.LD.hit_latency_hist | 9 90.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 10
system.ruby.LD.miss_latency_hist::bucket_size 256
system.ruby.LD.miss_latency_hist::max_bucket 2559
-system.ruby.LD.miss_latency_hist::samples 41
-system.ruby.LD.miss_latency_hist::mean 1048.902439
-system.ruby.LD.miss_latency_hist::gmean 1021.815979
-system.ruby.LD.miss_latency_hist::stdev 175.914866
-system.ruby.LD.miss_latency_hist | 1 2.44% 2.44% | 0 0.00% 2.44% | 0 0.00% 2.44% | 13 31.71% 34.15% | 26 63.41% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 41
+system.ruby.LD.miss_latency_hist::samples 36
+system.ruby.LD.miss_latency_hist::mean 1016.583333
+system.ruby.LD.miss_latency_hist::gmean 947.115995
+system.ruby.LD.miss_latency_hist::stdev 254.139824
+system.ruby.LD.miss_latency_hist | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 36
system.ruby.ST.latency_hist::bucket_size 256
system.ruby.ST.latency_hist::max_bucket 2559
-system.ruby.ST.latency_hist::samples 885
-system.ruby.ST.latency_hist::mean 891.871186
-system.ruby.ST.latency_hist::gmean 453.694429
-system.ruby.ST.latency_hist::stdev 379.187013
-system.ruby.ST.latency_hist | 131 14.80% 14.80% | 6 0.68% 15.48% | 5 0.56% 16.05% | 328 37.06% 53.11% | 377 42.60% 95.71% | 38 4.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 885
+system.ruby.ST.latency_hist::samples 846
+system.ruby.ST.latency_hist::mean 881.170213
+system.ruby.ST.latency_hist::gmean 402.465808
+system.ruby.ST.latency_hist::stdev 407.456674
+system.ruby.ST.latency_hist | 144 17.02% 17.02% | 6 0.71% 17.73% | 5 0.59% 18.32% | 247 29.20% 47.52% | 393 46.45% 93.97% | 51 6.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 846
system.ruby.ST.hit_latency_hist::bucket_size 256
system.ruby.ST.hit_latency_hist::max_bucket 2559
-system.ruby.ST.hit_latency_hist::samples 125
-system.ruby.ST.hit_latency_hist::mean 199.480000
-system.ruby.ST.hit_latency_hist::gmean 5.441959
-system.ruby.ST.hit_latency_hist::stdev 400.907933
-system.ruby.ST.hit_latency_hist | 101 80.80% 80.80% | 0 0.00% 80.80% | 0 0.00% 80.80% | 18 14.40% 95.20% | 4 3.20% 98.40% | 2 1.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 125
+system.ruby.ST.hit_latency_hist::samples 138
+system.ruby.ST.hit_latency_hist::mean 173.615942
+system.ruby.ST.hit_latency_hist::gmean 5.002563
+system.ruby.ST.hit_latency_hist::stdev 375.029660
+system.ruby.ST.hit_latency_hist | 115 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 16 11.59% 94.93% | 6 4.35% 99.28% | 1 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 138
system.ruby.ST.miss_latency_hist::bucket_size 256
system.ruby.ST.miss_latency_hist::max_bucket 2559
-system.ruby.ST.miss_latency_hist::samples 760
-system.ruby.ST.miss_latency_hist::mean 1005.751316
-system.ruby.ST.miss_latency_hist::gmean 939.114914
-system.ruby.ST.miss_latency_hist::stdev 221.956577
-system.ruby.ST.miss_latency_hist | 30 3.95% 3.95% | 6 0.79% 4.74% | 5 0.66% 5.39% | 310 40.79% 46.18% | 373 49.08% 95.26% | 36 4.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 760
-system.ruby.IFETCH.latency_hist::bucket_size 16
-system.ruby.IFETCH.latency_hist::max_bucket 159
-system.ruby.IFETCH.latency_hist::samples 48
-system.ruby.IFETCH.latency_hist::mean 56.625000
-system.ruby.IFETCH.latency_hist::gmean 49.781061
-system.ruby.IFETCH.latency_hist::stdev 21.417457
-system.ruby.IFETCH.latency_hist | 1 2.08% 2.08% | 4 8.33% 10.42% | 17 35.42% 45.83% | 1 2.08% 47.92% | 21 43.75% 91.67% | 3 6.25% 97.92% | 0 0.00% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 48
+system.ruby.ST.miss_latency_hist::samples 708
+system.ruby.ST.miss_latency_hist::mean 1019.083333
+system.ruby.ST.miss_latency_hist::gmean 946.557722
+system.ruby.ST.miss_latency_hist::stdev 233.252272
+system.ruby.ST.miss_latency_hist | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 708
+system.ruby.IFETCH.latency_hist::bucket_size 32
+system.ruby.IFETCH.latency_hist::max_bucket 319
+system.ruby.IFETCH.latency_hist::samples 54
+system.ruby.IFETCH.latency_hist::mean 69.555556
+system.ruby.IFETCH.latency_hist::gmean 55.256031
+system.ruby.IFETCH.latency_hist::stdev 50.686855
+system.ruby.IFETCH.latency_hist | 8 14.81% 14.81% | 15 27.78% 42.59% | 25 46.30% 88.89% | 0 0.00% 88.89% | 3 5.56% 94.44% | 0 0.00% 94.44% | 2 3.70% 98.15% | 0 0.00% 98.15% | 0 0.00% 98.15% | 1 1.85% 100.00%
+system.ruby.IFETCH.latency_hist::total 54
system.ruby.IFETCH.hit_latency_hist::bucket_size 4
system.ruby.IFETCH.hit_latency_hist::max_bucket 39
-system.ruby.IFETCH.hit_latency_hist::samples 5
-system.ruby.IFETCH.hit_latency_hist::mean 18.600000
-system.ruby.IFETCH.hit_latency_hist::gmean 12.255548
-system.ruby.IFETCH.hit_latency_hist::stdev 9.989995
-system.ruby.IFETCH.hit_latency_hist | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 5
-system.ruby.IFETCH.miss_latency_hist::bucket_size 16
-system.ruby.IFETCH.miss_latency_hist::max_bucket 159
-system.ruby.IFETCH.miss_latency_hist::samples 43
-system.ruby.IFETCH.miss_latency_hist::mean 61.046512
-system.ruby.IFETCH.miss_latency_hist::gmean 58.593153
-system.ruby.IFETCH.miss_latency_hist::stdev 17.654021
-system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 1 2.33% 41.86% | 21 48.84% 90.70% | 3 6.98% 97.67% | 0 0.00% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 43
+system.ruby.IFETCH.hit_latency_hist::samples 8
+system.ruby.IFETCH.hit_latency_hist::mean 20.625000
+system.ruby.IFETCH.hit_latency_hist::gmean 15.768384
+system.ruby.IFETCH.hit_latency_hist::stdev 8.052285
+system.ruby.IFETCH.hit_latency_hist | 1 12.50% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 1 12.50% 25.00% | 6 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 8
+system.ruby.IFETCH.miss_latency_hist::bucket_size 32
+system.ruby.IFETCH.miss_latency_hist::max_bucket 319
+system.ruby.IFETCH.miss_latency_hist::samples 46
+system.ruby.IFETCH.miss_latency_hist::mean 78.065217
+system.ruby.IFETCH.miss_latency_hist::gmean 68.721309
+system.ruby.IFETCH.miss_latency_hist::stdev 50.161252
+system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 46
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
-system.ruby.L1Cache.hit_mach_latency_hist::samples 98
+system.ruby.L1Cache.hit_mach_latency_hist::samples 106
system.ruby.L1Cache.hit_mach_latency_hist::mean 1
system.ruby.L1Cache.hit_mach_latency_hist::gmean 1
-system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 98 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total 98
+system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache.hit_mach_latency_hist::total 106
system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 256
system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 2559
-system.ruby.L2Cache.hit_mach_latency_hist::samples 43
-system.ruby.L2Cache.hit_mach_latency_hist::mean 602.953488
-system.ruby.L2Cache.hit_mach_latency_hist::gmean 256.823422
-system.ruby.L2Cache.hit_mach_latency_hist::stdev 489.931188
-system.ruby.L2Cache.hit_mach_latency_hist | 18 41.86% 41.86% | 0 0.00% 41.86% | 0 0.00% 41.86% | 19 44.19% 86.05% | 4 9.30% 95.35% | 2 4.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L2Cache.hit_mach_latency_hist::total 43
+system.ruby.L2Cache.hit_mach_latency_hist::samples 50
+system.ruby.L2Cache.hit_mach_latency_hist::mean 500.560000
+system.ruby.L2Cache.hit_mach_latency_hist::gmean 172.276482
+system.ruby.L2Cache.hit_mach_latency_hist::stdev 491.089092
+system.ruby.L2Cache.hit_mach_latency_hist | 26 52.00% 52.00% | 0 0.00% 52.00% | 0 0.00% 52.00% | 17 34.00% 86.00% | 6 12.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::total 50
system.ruby.Directory.miss_mach_latency_hist::bucket_size 256
system.ruby.Directory.miss_mach_latency_hist::max_bucket 2559
-system.ruby.Directory.miss_mach_latency_hist::samples 844
-system.ruby.Directory.miss_mach_latency_hist::mean 959.716825
-system.ruby.Directory.miss_mach_latency_hist::gmean 818.679034
-system.ruby.Directory.miss_mach_latency_hist::stdev 298.884250
-system.ruby.Directory.miss_mach_latency_hist | 74 8.77% 8.77% | 6 0.71% 9.48% | 5 0.59% 10.07% | 323 38.27% 48.34% | 399 47.27% 95.62% | 37 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist::total 844
+system.ruby.Directory.miss_mach_latency_hist::samples 790
+system.ruby.Directory.miss_mach_latency_hist::mean 964.175949
+system.ruby.Directory.miss_mach_latency_hist::gmean 812.519909
+system.ruby.Directory.miss_mach_latency_hist::stdev 316.811320
+system.ruby.Directory.miss_mach_latency_hist | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist::total 790
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 8
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 7
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 8
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 7
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 3
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 329.666667
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 116.879560
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 490.846548
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 334.333333
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 81.936099
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 537.513101
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 3
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 256
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 2559
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 41
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1048.902439
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1021.815979
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 175.914866
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 1 2.44% 2.44% | 0 0.00% 2.44% | 0 0.00% 2.44% | 13 31.71% 34.15% | 26 63.41% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total 41
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 36
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1016.583333
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 947.115995
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 254.139824
+system.ruby.LD.Directory.miss_type_mach_latency_hist | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total 36
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 89
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 98
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 89
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 98 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 98
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 256
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 2559
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 36
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 690.166667
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 358.678894
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 470.751163
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 12 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 18 50.00% 83.33% | 4 11.11% 94.44% | 2 5.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 36
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 40
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 596.525000
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 258.353536
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 485.549015
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 17 42.50% 42.50% | 0 0.00% 42.50% | 0 0.00% 42.50% | 16 40.00% 82.50% | 6 15.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 40
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 256
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 2559
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 760
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1005.751316
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 939.114914
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 221.956577
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 30 3.95% 3.95% | 6 0.79% 4.74% | 5 0.66% 5.39% | 310 40.79% 46.18% | 373 49.08% 95.26% | 36 4.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total 760
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 708
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1019.083333
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 946.557722
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 233.252272
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 708
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 1
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 4
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 39
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 4
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 23
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 22.930627
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 2
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 4
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 43
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.046512
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.593153
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 17.654021
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 1 2.33% 41.86% | 21 48.84% 90.70% | 3 6.98% 97.67% | 0 0.00% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 43
-system.ruby.Directory_Controller.GETX 762 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 84 0.00% 0.00%
-system.ruby.Directory_Controller.Lockdown 15 0.00% 0.00%
-system.ruby.Directory_Controller.Unlockdown 15 0.00% 0.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 7
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 23.428571
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 23.382968
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 1.511858
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 6 85.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 7
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 46
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 78.065217
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 68.721309
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 50.161252
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 46
+system.ruby.Directory_Controller.GETX 710 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 85 0.00% 0.00%
+system.ruby.Directory_Controller.Lockdown 17 0.00% 0.00%
+system.ruby.Directory_Controller.Unlockdown 17 0.00% 0.00%
system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00%
-system.ruby.Directory_Controller.Data_All_Tokens 768 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens 68 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 844 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 769 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 761 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETS 84 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETX 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Lockdown 3 0.00% 0.00%
+system.ruby.Directory_Controller.Data_All_Tokens 718 0.00% 0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens 65 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 790 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 719 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETX 708 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETS 83 0.00% 0.00%
+system.ruby.Directory_Controller.NO.GETX 2 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Lockdown 7 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens 768 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 68 0.00% 0.00%
-system.ruby.Directory_Controller.L.Unlockdown 15 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack 769 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data 12 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown 12 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 832 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 52 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 48 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 886 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 23140 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Shared 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens 895 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens 718 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 65 0.00% 0.00%
+system.ruby.Directory_Controller.L.Unlockdown 17 0.00% 0.00%
+system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack 719 0.00% 0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data 10 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown 10 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data 780 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 46 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 847 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 22253 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_Shared 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens 844 0.00% 0.00%
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 30 0.00% 0.00%
-system.ruby.L1Cache_Controller.Request_Timeout 23 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 878 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 44 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 796 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens 15 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 15 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 34 0.00% 0.00%
+system.ruby.L1Cache_Controller.Request_Timeout 61 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 829 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 39 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch 54 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Store 747 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens 14 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 14 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Store 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 8 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 79 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 3 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 75 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 797 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Store 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 519 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 79 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 748 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 551 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock 1 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 80 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10558 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 18 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10451 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 798 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10590 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 749 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 9900 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens 746 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout 21 0.00% 0.00%
-system.ruby.L1Cache_Controller.SM.Data_All_Tokens 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 591 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens 84 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 91 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 797 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 822 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout 55 0.00% 0.00%
+system.ruby.L1Cache_Controller.SM.Data_All_Tokens 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 516 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Shared 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens 82 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 93 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 748 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 770 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens 881 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 84 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens 833 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX 11 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 17 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 707 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 825 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 36 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 773 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 17 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 39 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.L1_GETX 2 0.00% 0.00%
system.ruby.L2Cache_Controller.O.L2_Replacement 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 35 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 821 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 38 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 769 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 14 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX 11 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS 6 0.00% 0.00%
---------- End Simulation Statistics ----------
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.l1_cntrl0.triggerQueue]
type=MessageBuffer
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:35:53
-gem5 started Nov 15 2015 14:36:13
-gem5 executing on ribera.cs.wisc.edu, pid 30617
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
+gem5 compiled Dec 11 2015 20:00:36
+gem5 started Dec 11 2015 20:01:07
+gem5 executing on zizzer, pid 31713
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 29631 because Ruby Tester completed
+Exiting @ tick 29561 because Ruby Tester completed
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29631 # Number of ticks simulated
-final_tick 29631 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 29561 # Number of ticks simulated
+final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 374763 # Simulator tick rate (ticks/s)
-host_mem_usage 446704 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 249798 # Simulator tick rate (ticks/s)
+host_mem_usage 387096 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55872 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55872 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49984 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49984 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 873 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 873 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 781 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 781 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1885592791 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1885592791 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1686881982 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1686881982 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3572474773 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 3572474773 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 873 # Number of read requests accepted
-system.mem_ctrls.writeReqs 781 # Number of write requests accepted
-system.mem_ctrls.readBursts 873 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 781 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45696 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 10176 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 41088 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55872 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49984 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 113 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 56000 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50560 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 50560 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 875 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 875 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 790 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 790 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1894387876 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1894387876 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1710361625 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1710361625 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 3604749501 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 3604749501 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 876 # Number of read requests accepted
+system.mem_ctrls.writeReqs 790 # Number of write requests accepted
+system.mem_ctrls.readBursts 876 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 790 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 9344 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 56064 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 50560 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 201 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 202 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 235 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 62 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 181 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 200 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 216 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 45 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 184 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 215 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 52 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 29604 # Total gap between requests
+system.mem_ctrls.totGap 29529 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 873 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 876 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 781 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 412 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 289 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 13 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 790 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 418 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 290 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 26 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 61 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 957.842697 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 925.208115 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 187.944921 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 4.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 1 1.12% 5.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 1 1.12% 6.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 5 5.62% 12.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1 1.12% 13.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 77 86.52% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 952.967033 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 882.848619 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 223.022742 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 2 2.20% 2.20% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 2 2.20% 4.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.20% 6.59% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 1 1.10% 7.69% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 2 2.20% 9.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1 1.10% 10.99% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 81 89.01% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.575000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.282559 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.868926 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 10 25.00% 25.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 14 35.00% 60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 10 25.00% 85.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 4 10.00% 95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 17.800000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.518113 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.824348 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 8 20.00% 20.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 16 40.00% 60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 8 20.00% 80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 6 15.00% 95.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::38-39 1 2.50% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.050000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.048573 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.220721 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 38 95.00% 95.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 2 5.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.268271 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.114013 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 36 90.00% 90.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 2 5.00% 95.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21 2 5.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8764 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 22330 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3570 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.27 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 8835 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 22705 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.10 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.27 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1542.17 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1386.66 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1885.59 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1686.88 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.10 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1580.46 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1411.59 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1896.55 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1710.36 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 22.88 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 12.05 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.83 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.73 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.84 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 637 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.68 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.36 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 17.90 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.39 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7026240 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5318784 # Energy for write commands per rank (pJ)
+system.mem_ctrls.busUtil 23.38 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 12.35 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 11.03 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 24.79 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 640 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 647 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.67 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 94.87 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 17.72 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.15 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 567000 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 315000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7176000 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 5432832 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 16099308 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 16101360 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 48600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 30877092 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1307.354221 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 31166472 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1319.439143 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 22841 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 22844 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 1005
-system.ruby.outstanding_req_hist::mean 15.587065
-system.ruby.outstanding_req_hist::gmean 15.474770
-system.ruby.outstanding_req_hist::stdev 1.278707
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 3 0.30% 0.80% | 3 0.30% 1.09% | 6 0.60% 1.69% | 5 0.50% 2.19% | 239 23.78% 25.97% | 744 74.03% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 1005
+system.ruby.outstanding_req_hist::samples 1027
+system.ruby.outstanding_req_hist::mean 15.566699
+system.ruby.outstanding_req_hist::gmean 15.456992
+system.ruby.outstanding_req_hist::stdev 1.265135
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.49% | 3 0.29% 0.78% | 3 0.29% 1.07% | 6 0.58% 1.66% | 3 0.29% 1.95% | 271 26.39% 28.33% | 736 71.67% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 1027
system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 990
-system.ruby.latency_hist::mean 463.933333
-system.ruby.latency_hist::gmean 252.592392
-system.ruby.latency_hist::stdev 232.151200
-system.ruby.latency_hist | 190 19.19% 19.19% | 9 0.91% 20.10% | 5 0.51% 20.61% | 142 14.34% 34.95% | 561 56.67% 91.62% | 42 4.24% 95.86% | 16 1.62% 97.47% | 25 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 990
-system.ruby.hit_latency_hist::bucket_size 128
-system.ruby.hit_latency_hist::max_bucket 1279
-system.ruby.hit_latency_hist::samples 120
-system.ruby.hit_latency_hist::mean 90.158333
-system.ruby.hit_latency_hist::gmean 4.686569
-system.ruby.hit_latency_hist::stdev 196.031167
-system.ruby.hit_latency_hist | 101 84.17% 84.17% | 0 0.00% 84.17% | 0 0.00% 84.17% | 8 6.67% 90.83% | 9 7.50% 98.33% | 2 1.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 120
+system.ruby.latency_hist::samples 1012
+system.ruby.latency_hist::mean 452.030632
+system.ruby.latency_hist::gmean 221.913062
+system.ruby.latency_hist::stdev 245.259624
+system.ruby.latency_hist | 227 22.43% 22.43% | 13 1.28% 23.72% | 6 0.59% 24.31% | 123 12.15% 36.46% | 525 51.88% 88.34% | 73 7.21% 95.55% | 35 3.46% 99.01% | 10 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 1012
+system.ruby.hit_latency_hist::bucket_size 64
+system.ruby.hit_latency_hist::max_bucket 639
+system.ruby.hit_latency_hist::samples 140
+system.ruby.hit_latency_hist::mean 75.100000
+system.ruby.hit_latency_hist::gmean 3.808266
+system.ruby.hit_latency_hist::stdev 173.693574
+system.ruby.hit_latency_hist | 117 83.57% 83.57% | 3 2.14% 85.71% | 1 0.71% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 4 2.86% 89.29% | 5 3.57% 92.86% | 8 5.71% 98.57% | 2 1.43% 100.00%
+system.ruby.hit_latency_hist::total 140
system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 870
-system.ruby.miss_latency_hist::mean 515.488506
-system.ruby.miss_latency_hist::gmean 437.780939
-system.ruby.miss_latency_hist::stdev 184.718401
-system.ruby.miss_latency_hist | 89 10.23% 10.23% | 9 1.03% 11.26% | 5 0.57% 11.84% | 134 15.40% 27.24% | 552 63.45% 90.69% | 40 4.60% 95.29% | 16 1.84% 97.13% | 25 2.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 870
-system.ruby.Directory.incomplete_times 870
+system.ruby.miss_latency_hist::samples 872
+system.ruby.miss_latency_hist::mean 512.547018
+system.ruby.miss_latency_hist::gmean 426.213857
+system.ruby.miss_latency_hist::stdev 196.222062
+system.ruby.miss_latency_hist | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 872
+system.ruby.Directory.incomplete_times 872
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 77 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 864 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 941 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 49 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 96 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 955 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 3 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses 873 # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses 912 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 82 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses 913 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 72 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 3 # Number of times a load aliased with a pending load
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 15.551281
-system.ruby.network.routers0.msg_count.Request_Control::2 874
-system.ruby.network.routers0.msg_count.Response_Data::4 872
-system.ruby.network.routers0.msg_count.Writeback_Data::5 781
-system.ruby.network.routers0.msg_count.Writeback_Control::2 865
-system.ruby.network.routers0.msg_count.Writeback_Control::3 866
-system.ruby.network.routers0.msg_count.Writeback_Control::5 84
-system.ruby.network.routers0.msg_count.Unblock_Control::5 869
-system.ruby.network.routers0.msg_bytes.Request_Control::2 6992
-system.ruby.network.routers0.msg_bytes.Response_Data::4 62784
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56232
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6920
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6928
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5 672
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6952
-system.ruby.network.routers1.percent_links_utilized 15.558030
-system.ruby.network.routers1.msg_count.Request_Control::2 874
-system.ruby.network.routers1.msg_count.Response_Data::4 873
-system.ruby.network.routers1.msg_count.Writeback_Data::5 781
-system.ruby.network.routers1.msg_count.Writeback_Control::2 865
-system.ruby.network.routers1.msg_count.Writeback_Control::3 866
-system.ruby.network.routers1.msg_count.Writeback_Control::5 84
-system.ruby.network.routers1.msg_count.Unblock_Control::5 869
-system.ruby.network.routers1.msg_bytes.Request_Control::2 6992
-system.ruby.network.routers1.msg_bytes.Response_Data::4 62856
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5 56232
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6920
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6928
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5 672
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6952
-system.ruby.network.routers2.percent_links_utilized 15.554656
-system.ruby.network.routers2.msg_count.Request_Control::2 874
-system.ruby.network.routers2.msg_count.Response_Data::4 873
-system.ruby.network.routers2.msg_count.Writeback_Data::5 781
-system.ruby.network.routers2.msg_count.Writeback_Control::2 865
-system.ruby.network.routers2.msg_count.Writeback_Control::3 866
-system.ruby.network.routers2.msg_count.Writeback_Control::5 84
-system.ruby.network.routers2.msg_count.Unblock_Control::5 869
-system.ruby.network.routers2.msg_bytes.Request_Control::2 6992
-system.ruby.network.routers2.msg_bytes.Response_Data::4 62856
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5 56232
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6920
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6928
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5 672
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6952
-system.ruby.network.msg_count.Request_Control 2622
-system.ruby.network.msg_count.Response_Data 2618
-system.ruby.network.msg_count.Writeback_Data 2343
+system.ruby.network.routers0.percent_links_utilized 15.685362
+system.ruby.network.routers0.msg_count.Request_Control::2 876
+system.ruby.network.routers0.msg_count.Response_Data::4 874
+system.ruby.network.routers0.msg_count.Writeback_Data::5 791
+system.ruby.network.routers0.msg_count.Writeback_Control::2 869
+system.ruby.network.routers0.msg_count.Writeback_Control::3 869
+system.ruby.network.routers0.msg_count.Writeback_Control::5 77
+system.ruby.network.routers0.msg_count.Unblock_Control::5 871
+system.ruby.network.routers0.msg_bytes.Request_Control::2 7008
+system.ruby.network.routers0.msg_bytes.Response_Data::4 62928
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56952
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6952
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6952
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.routers1.percent_links_utilized 15.679443
+system.ruby.network.routers1.msg_count.Request_Control::2 876
+system.ruby.network.routers1.msg_count.Response_Data::4 874
+system.ruby.network.routers1.msg_count.Writeback_Data::5 791
+system.ruby.network.routers1.msg_count.Writeback_Control::2 869
+system.ruby.network.routers1.msg_count.Writeback_Control::3 869
+system.ruby.network.routers1.msg_count.Writeback_Control::5 77
+system.ruby.network.routers1.msg_count.Unblock_Control::5 871
+system.ruby.network.routers1.msg_bytes.Request_Control::2 7008
+system.ruby.network.routers1.msg_bytes.Response_Data::4 62928
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5 56952
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6952
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6952
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5 616
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.routers2.percent_links_utilized 15.682825
+system.ruby.network.routers2.msg_count.Request_Control::2 876
+system.ruby.network.routers2.msg_count.Response_Data::4 874
+system.ruby.network.routers2.msg_count.Writeback_Data::5 791
+system.ruby.network.routers2.msg_count.Writeback_Control::2 869
+system.ruby.network.routers2.msg_count.Writeback_Control::3 869
+system.ruby.network.routers2.msg_count.Writeback_Control::5 77
+system.ruby.network.routers2.msg_count.Unblock_Control::5 871
+system.ruby.network.routers2.msg_bytes.Request_Control::2 7008
+system.ruby.network.routers2.msg_bytes.Response_Data::4 62928
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5 56952
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6952
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6952
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5 616
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.msg_count.Request_Control 2628
+system.ruby.network.msg_count.Response_Data 2622
+system.ruby.network.msg_count.Writeback_Data 2373
system.ruby.network.msg_count.Writeback_Control 5445
-system.ruby.network.msg_count.Unblock_Control 2607
-system.ruby.network.msg_byte.Request_Control 20976
-system.ruby.network.msg_byte.Response_Data 188496
-system.ruby.network.msg_byte.Writeback_Data 168696
+system.ruby.network.msg_count.Unblock_Control 2613
+system.ruby.network.msg_byte.Request_Control 21024
+system.ruby.network.msg_byte.Response_Data 188784
+system.ruby.network.msg_byte.Writeback_Data 170856
system.ruby.network.msg_byte.Writeback_Control 43560
-system.ruby.network.msg_byte.Unblock_Control 20856
-system.ruby.network.routers0.throttle0.link_utilization 14.699133
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 872
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 866
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 62784
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6928
-system.ruby.network.routers0.throttle1.link_utilization 16.403429
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 874
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 781
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 865
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 84
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 869
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 6992
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 56232
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6920
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 672
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6952
-system.ruby.network.routers1.throttle0.link_utilization 16.403429
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 874
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 781
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 865
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 84
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 869
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 6992
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 56232
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6920
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 672
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6952
-system.ruby.network.routers1.throttle1.link_utilization 14.712632
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 873
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 866
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 62856
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6928
-system.ruby.network.routers2.throttle0.link_utilization 14.705882
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 873
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 866
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 62856
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6928
-system.ruby.network.routers2.throttle1.link_utilization 16.403429
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 874
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 781
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 865
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 84
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 869
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 6992
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56232
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6920
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 672
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6952
+system.ruby.network.msg_byte.Unblock_Control 20904
+system.ruby.network.routers0.throttle0.link_utilization 14.774534
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 874
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 869
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 62928
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6952
+system.ruby.network.routers0.throttle1.link_utilization 16.596191
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 876
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 791
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 869
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 77
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 871
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 7008
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 56952
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6952
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 616
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.routers1.throttle0.link_utilization 16.584351
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 876
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 791
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 869
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 77
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 871
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 7008
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 56952
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6952
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 616
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.routers1.throttle1.link_utilization 14.774534
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 874
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 869
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 62928
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6952
+system.ruby.network.routers2.throttle0.link_utilization 14.774534
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 874
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 869
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 62928
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6952
+system.ruby.network.routers2.throttle1.link_utilization 16.591117
+system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 876
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 791
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 869
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 77
+system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 871
+system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 7008
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56952
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6952
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 616
+system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6968
system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
-system.ruby.LD.latency_hist::samples 52
-system.ruby.LD.latency_hist::mean 503.461538
-system.ruby.LD.latency_hist::gmean 317.197338
-system.ruby.LD.latency_hist::stdev 193.436970
-system.ruby.LD.latency_hist | 6 11.54% 11.54% | 0 0.00% 11.54% | 0 0.00% 11.54% | 8 15.38% 26.92% | 34 65.38% 92.31% | 2 3.85% 96.15% | 2 3.85% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 52
-system.ruby.LD.hit_latency_hist::bucket_size 8
-system.ruby.LD.hit_latency_hist::max_bucket 79
-system.ruby.LD.hit_latency_hist::samples 5
-system.ruby.LD.hit_latency_hist::mean 15.200000
-system.ruby.LD.hit_latency_hist::gmean 2.352158
-system.ruby.LD.hit_latency_hist::stdev 31.752165
-system.ruby.LD.hit_latency_hist | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 5
+system.ruby.LD.latency_hist::samples 43
+system.ruby.LD.latency_hist::mean 511.511628
+system.ruby.LD.latency_hist::gmean 293.373548
+system.ruby.LD.latency_hist::stdev 216.139767
+system.ruby.LD.latency_hist | 6 13.95% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 7 16.28% 30.23% | 23 53.49% 83.72% | 5 11.63% 95.35% | 1 2.33% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist::total 43
+system.ruby.LD.hit_latency_hist::bucket_size 1
+system.ruby.LD.hit_latency_hist::max_bucket 9
+system.ruby.LD.hit_latency_hist::samples 4
+system.ruby.LD.hit_latency_hist::mean 1
+system.ruby.LD.hit_latency_hist::gmean 1
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 4
system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
-system.ruby.LD.miss_latency_hist::samples 47
-system.ruby.LD.miss_latency_hist::mean 555.404255
-system.ruby.LD.miss_latency_hist::gmean 534.454462
-system.ruby.LD.miss_latency_hist::stdev 112.817024
-system.ruby.LD.miss_latency_hist | 1 2.13% 2.13% | 0 0.00% 2.13% | 0 0.00% 2.13% | 8 17.02% 19.15% | 34 72.34% 91.49% | 2 4.26% 95.74% | 2 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 47
+system.ruby.LD.miss_latency_hist::samples 39
+system.ruby.LD.miss_latency_hist::mean 563.871795
+system.ruby.LD.miss_latency_hist::gmean 525.399638
+system.ruby.LD.miss_latency_hist::stdev 146.240462
+system.ruby.LD.miss_latency_hist | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 39
system.ruby.ST.latency_hist::bucket_size 128
system.ruby.ST.latency_hist::max_bucket 1279
-system.ruby.ST.latency_hist::samples 887
-system.ruby.ST.latency_hist::mean 483.905299
-system.ruby.ST.latency_hist::gmean 275.171473
-system.ruby.ST.latency_hist::stdev 219.222904
-system.ruby.ST.latency_hist | 137 15.45% 15.45% | 7 0.79% 16.23% | 5 0.56% 16.80% | 134 15.11% 31.91% | 526 59.30% 91.21% | 39 4.40% 95.60% | 14 1.58% 97.18% | 25 2.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 887
-system.ruby.ST.hit_latency_hist::bucket_size 128
-system.ruby.ST.hit_latency_hist::max_bucket 1279
-system.ruby.ST.hit_latency_hist::samples 105
-system.ruby.ST.hit_latency_hist::mean 89.133333
-system.ruby.ST.hit_latency_hist::gmean 4.172115
-system.ruby.ST.hit_latency_hist::stdev 193.552272
-system.ruby.ST.hit_latency_hist | 88 83.81% 83.81% | 0 0.00% 83.81% | 0 0.00% 83.81% | 8 7.62% 91.43% | 8 7.62% 99.05% | 1 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 105
+system.ruby.ST.latency_hist::samples 910
+system.ruby.ST.latency_hist::mean 473.924176
+system.ruby.ST.latency_hist::gmean 243.035413
+system.ruby.ST.latency_hist::stdev 232.681347
+system.ruby.ST.latency_hist | 166 18.24% 18.24% | 11 1.21% 19.45% | 6 0.66% 20.11% | 116 12.75% 32.86% | 500 54.95% 87.80% | 68 7.47% 95.27% | 34 3.74% 99.01% | 9 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 910
+system.ruby.ST.hit_latency_hist::bucket_size 64
+system.ruby.ST.hit_latency_hist::max_bucket 639
+system.ruby.ST.hit_latency_hist::samples 126
+system.ruby.ST.hit_latency_hist::mean 74.587302
+system.ruby.ST.hit_latency_hist::gmean 3.636852
+system.ruby.ST.hit_latency_hist::stdev 172.646982
+system.ruby.ST.hit_latency_hist | 105 83.33% 83.33% | 3 2.38% 85.71% | 1 0.79% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 4 3.17% 89.68% | 5 3.97% 93.65% | 6 4.76% 98.41% | 2 1.59% 100.00%
+system.ruby.ST.hit_latency_hist::total 126
system.ruby.ST.miss_latency_hist::bucket_size 128
system.ruby.ST.miss_latency_hist::max_bucket 1279
-system.ruby.ST.miss_latency_hist::samples 782
-system.ruby.ST.miss_latency_hist::mean 536.911765
-system.ruby.ST.miss_latency_hist::gmean 482.920590
-system.ruby.ST.miss_latency_hist::stdev 160.516950
-system.ruby.ST.miss_latency_hist | 49 6.27% 6.27% | 7 0.90% 7.16% | 5 0.64% 7.80% | 126 16.11% 23.91% | 518 66.24% 90.15% | 38 4.86% 95.01% | 14 1.79% 96.80% | 25 3.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 782
-system.ruby.IFETCH.latency_hist::bucket_size 32
-system.ruby.IFETCH.latency_hist::max_bucket 319
-system.ruby.IFETCH.latency_hist::samples 48
-system.ruby.IFETCH.latency_hist::mean 53.604167
-system.ruby.IFETCH.latency_hist::gmean 40.463792
-system.ruby.IFETCH.latency_hist::stdev 35.834572
-system.ruby.IFETCH.latency_hist | 19 39.58% 39.58% | 18 37.50% 77.08% | 5 10.42% 87.50% | 4 8.33% 95.83% | 1 2.08% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 48
+system.ruby.ST.miss_latency_hist::samples 784
+system.ruby.ST.miss_latency_hist::mean 538.103316
+system.ruby.ST.miss_latency_hist::gmean 477.489826
+system.ruby.ST.miss_latency_hist::stdev 168.250948
+system.ruby.ST.miss_latency_hist | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 784
+system.ruby.IFETCH.latency_hist::bucket_size 16
+system.ruby.IFETCH.latency_hist::max_bucket 159
+system.ruby.IFETCH.latency_hist::samples 57
+system.ruby.IFETCH.latency_hist::mean 55
+system.ruby.IFETCH.latency_hist::gmean 40.845512
+system.ruby.IFETCH.latency_hist::stdev 30.808162
+system.ruby.IFETCH.latency_hist | 8 14.04% 14.04% | 6 10.53% 24.56% | 1 1.75% 26.32% | 27 47.37% 73.68% | 9 15.79% 89.47% | 3 5.26% 94.74% | 1 1.75% 96.49% | 0 0.00% 96.49% | 0 0.00% 96.49% | 2 3.51% 100.00%
+system.ruby.IFETCH.latency_hist::total 57
system.ruby.IFETCH.hit_latency_hist::bucket_size 2
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
-system.ruby.IFETCH.hit_latency_hist::samples 7
-system.ruby.IFETCH.hit_latency_hist::mean 9.571429
-system.ruby.IFETCH.hit_latency_hist::gmean 7.809483
-system.ruby.IFETCH.hit_latency_hist::stdev 3.779645
-system.ruby.IFETCH.hit_latency_hist | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 6 85.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 7
-system.ruby.IFETCH.miss_latency_hist::bucket_size 32
-system.ruby.IFETCH.miss_latency_hist::max_bucket 319
-system.ruby.IFETCH.miss_latency_hist::samples 41
-system.ruby.IFETCH.miss_latency_hist::mean 61.121951
-system.ruby.IFETCH.miss_latency_hist::gmean 53.585201
-system.ruby.IFETCH.miss_latency_hist::stdev 33.308554
-system.ruby.IFETCH.miss_latency_hist | 12 29.27% 29.27% | 18 43.90% 73.17% | 5 12.20% 85.37% | 4 9.76% 95.12% | 1 2.44% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 41
-system.ruby.FLUSH.latency_hist::bucket_size 128
-system.ruby.FLUSH.latency_hist::max_bucket 1279
-system.ruby.FLUSH.latency_hist::samples 3
-system.ruby.FLUSH.latency_hist::mean 439
-system.ruby.FLUSH.latency_hist::gmean 262.927467
-system.ruby.FLUSH.latency_hist::stdev 342.057013
-system.ruby.FLUSH.latency_hist | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.FLUSH.latency_hist::total 3
-system.ruby.FLUSH.hit_latency_hist::bucket_size 128
-system.ruby.FLUSH.hit_latency_hist::max_bucket 1279
-system.ruby.FLUSH.hit_latency_hist::samples 3
-system.ruby.FLUSH.hit_latency_hist::mean 439
-system.ruby.FLUSH.hit_latency_hist::gmean 262.927467
-system.ruby.FLUSH.hit_latency_hist::stdev 342.057013
-system.ruby.FLUSH.hit_latency_hist | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.FLUSH.hit_latency_hist::total 3
-system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 128
-system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 1279
-system.ruby.L1Cache.hit_mach_latency_hist::samples 81
-system.ruby.L1Cache.hit_mach_latency_hist::mean 17.222222
-system.ruby.L1Cache.hit_mach_latency_hist::gmean 1.229203
-system.ruby.L1Cache.hit_mach_latency_hist::stdev 99.261145
-system.ruby.L1Cache.hit_mach_latency_hist | 79 97.53% 97.53% | 0 0.00% 97.53% | 0 0.00% 97.53% | 0 0.00% 97.53% | 1 1.23% 98.77% | 1 1.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.hit_mach_latency_hist::total 81
-system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 128
-system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 1279
+system.ruby.IFETCH.hit_latency_hist::samples 8
+system.ruby.IFETCH.hit_latency_hist::mean 7.250000
+system.ruby.IFETCH.hit_latency_hist::gmean 4.475797
+system.ruby.IFETCH.hit_latency_hist::stdev 5.175492
+system.ruby.IFETCH.hit_latency_hist | 3 37.50% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 5 62.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 8
+system.ruby.IFETCH.miss_latency_hist::bucket_size 16
+system.ruby.IFETCH.miss_latency_hist::max_bucket 159
+system.ruby.IFETCH.miss_latency_hist::samples 49
+system.ruby.IFETCH.miss_latency_hist::mean 62.795918
+system.ruby.IFETCH.miss_latency_hist::gmean 58.603527
+system.ruby.IFETCH.miss_latency_hist::stdev 25.717196
+system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 49
+system.ruby.FLUSH.latency_hist::bucket_size 64
+system.ruby.FLUSH.latency_hist::max_bucket 639
+system.ruby.FLUSH.latency_hist::samples 2
+system.ruby.FLUSH.latency_hist::mean 527
+system.ruby.FLUSH.latency_hist::gmean 526.885187
+system.ruby.FLUSH.latency_hist::stdev 15.556349
+system.ruby.FLUSH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.FLUSH.latency_hist::total 2
+system.ruby.FLUSH.hit_latency_hist::bucket_size 64
+system.ruby.FLUSH.hit_latency_hist::max_bucket 639
+system.ruby.FLUSH.hit_latency_hist::samples 2
+system.ruby.FLUSH.hit_latency_hist::mean 527
+system.ruby.FLUSH.hit_latency_hist::gmean 526.885187
+system.ruby.FLUSH.hit_latency_hist::stdev 15.556349
+system.ruby.FLUSH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.FLUSH.hit_latency_hist::total 2
+system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 64
+system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 639
+system.ruby.L1Cache.hit_mach_latency_hist::samples 101
+system.ruby.L1Cache.hit_mach_latency_hist::mean 11.415842
+system.ruby.L1Cache.hit_mach_latency_hist::gmean 1.132128
+system.ruby.L1Cache.hit_mach_latency_hist::stdev 73.663867
+system.ruby.L1Cache.hit_mach_latency_hist | 99 98.02% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 2 1.98% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache.hit_mach_latency_hist::total 101
+system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 64
+system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 639
system.ruby.L2Cache.hit_mach_latency_hist::samples 39
-system.ruby.L2Cache.hit_mach_latency_hist::mean 241.641026
-system.ruby.L2Cache.hit_mach_latency_hist::gmean 75.514116
-system.ruby.L2Cache.hit_mach_latency_hist::stdev 254.377929
-system.ruby.L2Cache.hit_mach_latency_hist | 22 56.41% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 8 20.51% 76.92% | 8 20.51% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L2Cache.hit_mach_latency_hist::mean 240.025641
+system.ruby.L2Cache.hit_mach_latency_hist::gmean 88.122529
+system.ruby.L2Cache.hit_mach_latency_hist::stdev 239.543259
+system.ruby.L2Cache.hit_mach_latency_hist | 18 46.15% 46.15% | 3 7.69% 53.85% | 1 2.56% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 4 10.26% 66.67% | 5 12.82% 79.49% | 6 15.38% 94.87% | 2 5.13% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist::total 39
system.ruby.Directory.miss_mach_latency_hist::bucket_size 128
system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279
-system.ruby.Directory.miss_mach_latency_hist::samples 870
-system.ruby.Directory.miss_mach_latency_hist::mean 515.488506
-system.ruby.Directory.miss_mach_latency_hist::gmean 437.780939
-system.ruby.Directory.miss_mach_latency_hist::stdev 184.718401
-system.ruby.Directory.miss_mach_latency_hist | 89 10.23% 10.23% | 9 1.03% 11.26% | 5 0.57% 11.84% | 134 15.40% 27.24% | 552 63.45% 90.69% | 40 4.60% 95.29% | 16 1.84% 97.13% | 25 2.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist::total 870
+system.ruby.Directory.miss_mach_latency_hist::samples 872
+system.ruby.Directory.miss_mach_latency_hist::mean 512.547018
+system.ruby.Directory.miss_mach_latency_hist::gmean 426.213857
+system.ruby.Directory.miss_mach_latency_hist::stdev 196.222062
+system.ruby.Directory.miss_mach_latency_hist | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist::total 872
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 4
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 4
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 8
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 79
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 72
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 72
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev nan
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 47
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 555.404255
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 534.454462
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 112.817024
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 1 2.13% 2.13% | 0 0.00% 2.13% | 0 0.00% 2.13% | 8 17.02% 19.15% | 34 72.34% 91.49% | 2 4.26% 95.74% | 2 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total 47
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 39
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 563.871795
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 525.399638
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 146.240462
+system.ruby.LD.Directory.miss_type_mach_latency_hist | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total 39
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 73
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 92
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 73 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 73
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 1279
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 32
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 290.187500
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 108.528557
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 256.247290
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 15 46.88% 46.88% | 0 0.00% 46.88% | 0 0.00% 46.88% | 8 25.00% 71.88% | 8 25.00% 96.88% | 1 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 32
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 92
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 64
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 639
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 34
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 273.705882
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 119.669415
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 238.660724
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 13 38.24% 38.24% | 3 8.82% 47.06% | 1 2.94% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 11.76% 61.76% | 5 14.71% 76.47% | 6 17.65% 94.12% | 2 5.88% 100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 34
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 782
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 536.911765
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 482.920590
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 160.516950
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 49 6.27% 6.27% | 7 0.90% 7.16% | 5 0.64% 7.80% | 126 16.11% 23.91% | 518 66.24% 90.15% | 38 4.86% 95.01% | 14 1.79% 96.80% | 25 3.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total 782
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 784
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 538.103316
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 477.489826
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 168.250948
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 784
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 3
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::stdev nan
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 1
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 3
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 6
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 5
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 11
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 6
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 41
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.121951
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 53.585201
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 33.308554
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 12 29.27% 29.27% | 18 43.90% 73.17% | 5 12.20% 85.37% | 4 9.76% 95.12% | 1 2.44% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 41
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size 128
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket 1279
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 3
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 439
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 262.927467
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 342.057013
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 3
-system.ruby.Directory_Controller.GETX 782 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 93 0.00% 0.00%
-system.ruby.Directory_Controller.PUT 1119 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockM 869 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean 84 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 781 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 873 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 781 0.00% 0.00%
-system.ruby.Directory_Controller.GETF 3 0.00% 0.00%
-system.ruby.Directory_Controller.PUTF 3 0.00% 0.00%
-system.ruby.Directory_Controller.NO.PUT 862 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETF 1 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETX 782 0.00% 0.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 5
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 62.795918
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.603527
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 25.717196
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size 64
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket 639
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 2
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 527
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 526.885187
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 15.556349
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 2
+system.ruby.Directory_Controller.GETX 785 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 90 0.00% 0.00%
+system.ruby.Directory_Controller.PUT 1118 0.00% 0.00%
+system.ruby.Directory_Controller.UnblockM 871 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 790 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 874 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 790 0.00% 0.00%
+system.ruby.Directory_Controller.GETF 2 0.00% 0.00%
+system.ruby.Directory_Controller.PUTF 2 0.00% 0.00%
+system.ruby.Directory_Controller.NO.PUT 867 0.00% 0.00%
+system.ruby.Directory_Controller.E.GETX 785 0.00% 0.00%
system.ruby.Directory_Controller.E.GETS 89 0.00% 0.00%
system.ruby.Directory_Controller.E.GETF 2 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.PUT 257 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM 869 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data 871 0.00% 0.00%
-system.ruby.Directory_Controller.WB.GETS 3 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 84 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 781 0.00% 0.00%
-system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack 781 0.00% 0.00%
-system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.PUT 251 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM 871 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data 872 0.00% 0.00%
+system.ruby.Directory_Controller.WB.GETS 1 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 790 0.00% 0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack 790 0.00% 0.00%
+system.ruby.Directory_Controller.NO_F.PUTF 2 0.00% 0.00%
system.ruby.Directory_Controller.NO_F_W.Memory_Data 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 50 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 916 0.00% 0.00%
-system.ruby.L1Cache_Controller.L2_Replacement 865 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_to_L2 18208 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 44 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 59 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 942 0.00% 0.00%
+system.ruby.L1Cache_Controller.L2_Replacement 867 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_to_L2 18224 0.00% 0.00%
system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 34 0.00% 0.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 872 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 865 0.00% 0.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers 872 0.00% 0.00%
-system.ruby.L1Cache_Controller.Flush_line 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.Block_Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 42 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 784 0.00% 0.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.Complete_L2_to_L1 39 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 874 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 869 0.00% 0.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers 874 0.00% 0.00%
+system.ruby.L1Cache_Controller.Flush_line 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 40 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 49 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 785 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Flush_line 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement 82 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2 88 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement 76 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2 85 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 9 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 73 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement 783 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2 819 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 29 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.MR.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MR.Store 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Ifetch 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Store 28 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Flush_line 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2 10628 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data 782 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2 348 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 91 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement 791 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_to_L2 823 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 25 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.MR.Store 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.MR.L1_to_L2 116 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMR.Ifetch 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMR.Store 25 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMR.L1_to_L2 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_to_L2 10757 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data 784 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_to_L2 187 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 88 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5413 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 782 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2 644 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5531 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 784 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_to_L2 475 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Exclusive_Data 88 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 862 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.Store 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2 56 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 5 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.Store 23 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2 159 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 35 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_F.Block_Ack 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 867 0.00% 0.00%
+system.ruby.L1Cache_Controller.MT.Store 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.MT.L1_to_L2 118 0.00% 0.00%
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMT.Ifetch 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMT.Store 22 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMT.L1_to_L2 130 0.00% 0.00%
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 2 0.00% 0.00%
system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 2 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 2 0.00% 0.00%
num_cpus=1
system=system
wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.dvfs_handler]
type=DVFSHandler
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
max_outstanding_requests=16
+no_retry_on_stall=true
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
using_network_tester=false
using_ruby_tester=true
version=0
-slave=system.cpu.cpuDataPort[0] system.cpu.cpuInstPort[0]
+slave=system.cpu.cpuInstDataPort[0]
[system.ruby.memctrl_clk_domain]
type=DerivedClockDomain
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:36
-gem5 executing on ribera.cs.wisc.edu, pid 29062
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:29
+gem5 executing on zizzer, pid 26182
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 37801 because Ruby Tester completed
+Exiting @ tick 37741 because Ruby Tester completed
---------- Begin Simulation Statistics ----------
sim_seconds 0.000038 # Number of seconds simulated
-sim_ticks 37801 # Number of ticks simulated
-final_tick 37801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 37741 # Number of ticks simulated
+final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 573737 # Simulator tick rate (ticks/s)
-host_mem_usage 444464 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 420656 # Simulator tick rate (ticks/s)
+host_mem_usage 384732 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 61504 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 61504 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 61312 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 61312 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 961 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 961 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 958 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 958 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1627046904 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1627046904 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1621967673 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1621967673 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3249014576 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 3249014576 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 961 # Number of read requests accepted
-system.mem_ctrls.writeReqs 958 # Number of write requests accepted
-system.mem_ctrls.readBursts 961 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 958 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 53184 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 8320 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 52736 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 61504 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 61312 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 60992 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60800 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 60800 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 953 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 953 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 950 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 950 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1616067407 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1616067407 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1610980101 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1610980101 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 3227047508 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 3227047508 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 953 # Number of read requests accepted
+system.mem_ctrls.writeReqs 950 # Number of write requests accepted
+system.mem_ctrls.readBursts 953 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 950 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 52800 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 8192 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 51456 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 60992 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 60800 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 284 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 229 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 263 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 55 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 259 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 251 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 261 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 54 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 279 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 228 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 259 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 58 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 255 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 246 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 250 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 53 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 37739 # Total gap between requests
+system.mem_ctrls.totGap 37680 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 961 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 953 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 958 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 472 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 358 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 950 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 469 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 355 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 53 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 54 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 51 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 51 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 51 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 53 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 73 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 70 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 109 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 961.174312 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 916.871548 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 196.872813 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 3 2.75% 2.75% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 2 1.83% 4.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 1 0.92% 5.50% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 3 2.75% 8.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2 1.83% 10.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3 2.75% 12.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 95 87.16% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 109 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 51 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 16.176471 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 16.043156 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 2.718131 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 10 19.61% 19.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 40 78.43% 98.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 1.96% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 51 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 51 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.156863 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.152882 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.367290 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 43 84.31% 84.31% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 8 15.69% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 51 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 10313 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26102 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4155 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.41 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 107 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 956.411215 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 902.763557 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 202.735209 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 1 0.93% 0.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 3 2.80% 3.74% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 1 0.93% 4.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2 1.87% 6.54% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 3.74% 10.28% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 2 1.87% 12.15% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1 0.93% 13.08% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 93 86.92% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 107 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 50 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 16.240000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 16.100110 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 2.766859 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 11 22.00% 22.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 37 74.00% 96.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 1 2.00% 98.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 2.00% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 50 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 50 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.080000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.077788 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.274048 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 46 92.00% 92.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 4 8.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 50 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 10350 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 26025 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4125 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.55 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.41 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1406.95 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1395.10 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1627.05 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1621.97 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.55 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1399.01 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1363.40 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1616.07 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1610.98 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 21.89 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 10.99 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.90 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.72 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 725 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 817 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 96.57 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 19.67 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.95 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 8561280 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 7039872 # Energy for write commands per rank (pJ)
+system.mem_ctrls.busUtil 21.58 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 10.93 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 10.65 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.73 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 26.18 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 719 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 799 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.15 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 95.92 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 19.80 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.56 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 687960 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 382200 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 8548800 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6822144 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 21405780 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 65400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 40188492 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1279.725258 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 39946524 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1272.020252 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 1919 # delay histogram for all message
-system.ruby.delayHist::mean 0.195935 # delay histogram for all message
-system.ruby.delayHist::stdev 1.060802 # delay histogram for all message
-system.ruby.delayHist | 1855 96.66% 96.66% | 0 0.00% 96.66% | 1 0.05% 96.72% | 0 0.00% 96.72% | 2 0.10% 96.82% | 0 0.00% 96.82% | 61 3.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 1919 # delay histogram for all message
+system.ruby.delayHist::samples 1903 # delay histogram for all message
+system.ruby.delayHist::mean 0.196532 # delay histogram for all message
+system.ruby.delayHist::stdev 1.062331 # delay histogram for all message
+system.ruby.delayHist | 1839 96.64% 96.64% | 0 0.00% 96.64% | 2 0.11% 96.74% | 0 0.00% 96.74% | 1 0.05% 96.79% | 0 0.00% 96.79% | 61 3.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 1903 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 1017
-system.ruby.outstanding_req_hist::mean 15.607670
-system.ruby.outstanding_req_hist::gmean 15.500838
-system.ruby.outstanding_req_hist::stdev 1.236128
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 3 0.29% 1.38% | 3 0.29% 1.67% | 233 22.91% 24.58% | 767 75.42% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 1017
+system.ruby.outstanding_req_hist::samples 1005
+system.ruby.outstanding_req_hist::mean 15.609950
+system.ruby.outstanding_req_hist::gmean 15.502410
+system.ruby.outstanding_req_hist::stdev 1.236521
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.09% | 3 0.30% 1.39% | 4 0.40% 1.79% | 233 23.18% 24.98% | 754 75.02% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 1005
system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 1003
-system.ruby.latency_hist::mean 586.918245
-system.ruby.latency_hist::gmean 576.888257
-system.ruby.latency_hist::stdev 98.601394
-system.ruby.latency_hist | 2 0.20% 0.20% | 9 0.90% 1.10% | 6 0.60% 1.69% | 138 13.76% 15.45% | 667 66.50% 81.95% | 127 12.66% 94.62% | 42 4.19% 98.80% | 12 1.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 1003
+system.ruby.latency_hist::samples 992
+system.ruby.latency_hist::mean 594.351815
+system.ruby.latency_hist::gmean 584.578373
+system.ruby.latency_hist::stdev 96.099439
+system.ruby.latency_hist | 2 0.20% 0.20% | 9 0.91% 1.11% | 6 0.60% 1.71% | 111 11.19% 12.90% | 654 65.93% 78.83% | 154 15.52% 94.35% | 49 4.94% 99.29% | 7 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 992
system.ruby.hit_latency_hist::bucket_size 128
system.ruby.hit_latency_hist::max_bucket 1279
-system.ruby.hit_latency_hist::samples 42
-system.ruby.hit_latency_hist::mean 502
-system.ruby.hit_latency_hist::gmean 497.343988
-system.ruby.hit_latency_hist::stdev 68.792371
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.38% 2.38% | 20 47.62% 50.00% | 20 47.62% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 42
+system.ruby.hit_latency_hist::samples 39
+system.ruby.hit_latency_hist::mean 492.692308
+system.ruby.hit_latency_hist::gmean 488.844837
+system.ruby.hit_latency_hist::stdev 62.931522
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.56% 2.56% | 22 56.41% 58.97% | 15 38.46% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 39
system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 961
-system.ruby.miss_latency_hist::mean 590.629553
-system.ruby.miss_latency_hist::gmean 580.641121
-system.ruby.miss_latency_hist::stdev 98.062205
-system.ruby.miss_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.14% | 5 0.52% 1.66% | 118 12.28% 13.94% | 647 67.33% 81.27% | 126 13.11% 94.38% | 42 4.37% 98.75% | 12 1.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 961
-system.ruby.Directory.incomplete_times 961
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 963 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 1005 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 127 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
+system.ruby.miss_latency_hist::samples 953
+system.ruby.miss_latency_hist::mean 598.512067
+system.ruby.miss_latency_hist::gmean 588.872583
+system.ruby.miss_latency_hist::stdev 94.945507
+system.ruby.miss_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 953
+system.ruby.Directory.incomplete_times 953
+system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses 955 # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses 994 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 129 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 12.694109
-system.ruby.network.routers0.msg_count.Control::2 961
-system.ruby.network.routers0.msg_count.Data::2 959
-system.ruby.network.routers0.msg_count.Response_Data::4 961
-system.ruby.network.routers0.msg_count.Writeback_Control::3 958
-system.ruby.network.routers0.msg_bytes.Control::2 7688
-system.ruby.network.routers0.msg_bytes.Data::2 69048
-system.ruby.network.routers0.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers1.percent_links_utilized 12.691463
-system.ruby.network.routers1.msg_count.Control::2 961
-system.ruby.network.routers1.msg_count.Data::2 958
-system.ruby.network.routers1.msg_count.Response_Data::4 961
-system.ruby.network.routers1.msg_count.Writeback_Control::3 958
-system.ruby.network.routers1.msg_bytes.Control::2 7688
-system.ruby.network.routers1.msg_bytes.Data::2 68976
-system.ruby.network.routers1.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers2.percent_links_utilized 12.691463
-system.ruby.network.routers2.msg_count.Control::2 961
-system.ruby.network.routers2.msg_count.Data::2 958
-system.ruby.network.routers2.msg_count.Response_Data::4 961
-system.ruby.network.routers2.msg_count.Writeback_Control::3 958
-system.ruby.network.routers2.msg_bytes.Control::2 7688
-system.ruby.network.routers2.msg_bytes.Data::2 68976
-system.ruby.network.routers2.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.msg_count.Control 2883
-system.ruby.network.msg_count.Data 2875
-system.ruby.network.msg_count.Response_Data 2883
-system.ruby.network.msg_count.Writeback_Control 2874
-system.ruby.network.msg_byte.Control 23064
-system.ruby.network.msg_byte.Data 207000
-system.ruby.network.msg_byte.Response_Data 207576
-system.ruby.network.msg_byte.Writeback_Control 22992
-system.ruby.network.routers0.throttle0.link_utilization 12.707336
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 961
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 958
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers0.throttle1.link_utilization 12.680881
-system.ruby.network.routers0.throttle1.msg_count.Control::2 961
-system.ruby.network.routers0.throttle1.msg_count.Data::2 959
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7688
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 69048
-system.ruby.network.routers1.throttle0.link_utilization 12.675591
-system.ruby.network.routers1.throttle0.msg_count.Control::2 961
-system.ruby.network.routers1.throttle0.msg_count.Data::2 958
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7688
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 68976
-system.ruby.network.routers1.throttle1.link_utilization 12.707336
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 961
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 958
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers2.throttle0.link_utilization 12.707336
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 961
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 958
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 69192
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7664
-system.ruby.network.routers2.throttle1.link_utilization 12.675591
-system.ruby.network.routers2.throttle1.msg_count.Control::2 961
-system.ruby.network.routers2.throttle1.msg_count.Data::2 958
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7688
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 68976
+system.ruby.network.routers0.percent_links_utilized 12.606979
+system.ruby.network.routers0.msg_count.Control::2 953
+system.ruby.network.routers0.msg_count.Data::2 951
+system.ruby.network.routers0.msg_count.Response_Data::4 953
+system.ruby.network.routers0.msg_count.Writeback_Control::3 950
+system.ruby.network.routers0.msg_bytes.Control::2 7624
+system.ruby.network.routers0.msg_bytes.Data::2 68472
+system.ruby.network.routers0.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers1.percent_links_utilized 12.605654
+system.ruby.network.routers1.msg_count.Control::2 953
+system.ruby.network.routers1.msg_count.Data::2 950
+system.ruby.network.routers1.msg_count.Response_Data::4 953
+system.ruby.network.routers1.msg_count.Writeback_Control::3 950
+system.ruby.network.routers1.msg_bytes.Control::2 7624
+system.ruby.network.routers1.msg_bytes.Data::2 68400
+system.ruby.network.routers1.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.percent_links_utilized 12.605654
+system.ruby.network.routers2.msg_count.Control::2 953
+system.ruby.network.routers2.msg_count.Data::2 950
+system.ruby.network.routers2.msg_count.Response_Data::4 953
+system.ruby.network.routers2.msg_count.Writeback_Control::3 950
+system.ruby.network.routers2.msg_bytes.Control::2 7624
+system.ruby.network.routers2.msg_bytes.Data::2 68400
+system.ruby.network.routers2.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.msg_count.Control 2859
+system.ruby.network.msg_count.Data 2851
+system.ruby.network.msg_count.Response_Data 2859
+system.ruby.network.msg_count.Writeback_Control 2850
+system.ruby.network.msg_byte.Control 22872
+system.ruby.network.msg_byte.Data 205272
+system.ruby.network.msg_byte.Response_Data 205848
+system.ruby.network.msg_byte.Writeback_Control 22800
+system.ruby.network.routers0.throttle0.link_utilization 12.621552
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 953
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 950
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers0.throttle1.link_utilization 12.592406
+system.ruby.network.routers0.throttle1.msg_count.Control::2 953
+system.ruby.network.routers0.throttle1.msg_count.Data::2 951
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7624
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2 68472
+system.ruby.network.routers1.throttle0.link_utilization 12.589756
+system.ruby.network.routers1.throttle0.msg_count.Control::2 953
+system.ruby.network.routers1.throttle0.msg_count.Data::2 950
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7624
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2 68400
+system.ruby.network.routers1.throttle1.link_utilization 12.621552
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 953
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 950
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.throttle0.link_utilization 12.621552
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 953
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 950
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 68616
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.throttle1.link_utilization 12.589756
+system.ruby.network.routers2.throttle1.msg_count.Control::2 953
+system.ruby.network.routers2.throttle1.msg_count.Data::2 950
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7624
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2 68400
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 961 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 961 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 961 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 953 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 953 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 953 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 958 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.392484 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 1.475833 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 894 93.32% 93.32% | 0 0.00% 93.32% | 1 0.10% 93.42% | 0 0.00% 93.42% | 2 0.21% 93.63% | 0 0.00% 93.63% | 61 6.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 958 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 950 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.393684 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 1.477888 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 886 93.26% 93.26% | 0 0.00% 93.26% | 2 0.21% 93.47% | 0 0.00% 93.47% | 1 0.11% 93.58% | 0 0.00% 93.58% | 61 6.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 950 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
-system.ruby.LD.latency_hist::samples 47
-system.ruby.LD.latency_hist::mean 581.170213
-system.ruby.LD.latency_hist::gmean 573.743591
-system.ruby.LD.latency_hist::stdev 97.598850
-system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 23.40% 23.40% | 29 61.70% 85.11% | 4 8.51% 93.62% | 2 4.26% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 47
-system.ruby.LD.hit_latency_hist::bucket_size 64
-system.ruby.LD.hit_latency_hist::max_bucket 639
-system.ruby.LD.hit_latency_hist::samples 1
-system.ruby.LD.hit_latency_hist::mean 386
-system.ruby.LD.hit_latency_hist::gmean 386.000000
-system.ruby.LD.hit_latency_hist::stdev nan
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 1
+system.ruby.LD.latency_hist::samples 50
+system.ruby.LD.latency_hist::mean 620.660000
+system.ruby.LD.latency_hist::gmean 616.355454
+system.ruby.LD.latency_hist::stdev 75.297399
+system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist::total 50
system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
-system.ruby.LD.miss_latency_hist::samples 46
-system.ruby.LD.miss_latency_hist::mean 585.413043
-system.ruby.LD.miss_latency_hist::gmean 578.708439
-system.ruby.LD.miss_latency_hist::stdev 94.193082
-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 21.74% 21.74% | 29 63.04% 84.78% | 4 8.70% 93.48% | 2 4.35% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 46
+system.ruby.LD.miss_latency_hist::samples 50
+system.ruby.LD.miss_latency_hist::mean 620.660000
+system.ruby.LD.miss_latency_hist::gmean 616.355454
+system.ruby.LD.miss_latency_hist::stdev 75.297399
+system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 50
system.ruby.ST.latency_hist::bucket_size 128
system.ruby.ST.latency_hist::max_bucket 1279
-system.ruby.ST.latency_hist::samples 903
-system.ruby.ST.latency_hist::mean 587.266888
-system.ruby.ST.latency_hist::gmean 576.890095
-system.ruby.ST.latency_hist::stdev 99.206221
-system.ruby.ST.latency_hist | 2 0.22% 0.22% | 9 1.00% 1.22% | 6 0.66% 1.88% | 116 12.85% 14.73% | 602 66.67% 81.40% | 120 13.29% 94.68% | 37 4.10% 98.78% | 11 1.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 903
+system.ruby.ST.latency_hist::samples 892
+system.ruby.ST.latency_hist::mean 591.263453
+system.ruby.ST.latency_hist::gmean 581.152835
+system.ruby.ST.latency_hist::stdev 96.524225
+system.ruby.ST.latency_hist | 2 0.22% 0.22% | 9 1.01% 1.23% | 6 0.67% 1.91% | 103 11.55% 13.45% | 591 66.26% 79.71% | 135 15.13% 94.84% | 39 4.37% 99.22% | 7 0.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 892
system.ruby.ST.hit_latency_hist::bucket_size 128
system.ruby.ST.hit_latency_hist::max_bucket 1279
-system.ruby.ST.hit_latency_hist::samples 41
-system.ruby.ST.hit_latency_hist::mean 504.829268
-system.ruby.ST.hit_latency_hist::gmean 500.427879
-system.ruby.ST.hit_latency_hist::stdev 67.127454
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.44% 2.44% | 19 46.34% 48.78% | 20 48.78% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 41
+system.ruby.ST.hit_latency_hist::samples 38
+system.ruby.ST.hit_latency_hist::mean 491.526316
+system.ruby.ST.hit_latency_hist::gmean 487.637688
+system.ruby.ST.hit_latency_hist::stdev 63.347918
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.63% 2.63% | 22 57.89% 60.53% | 14 36.84% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 38
system.ruby.ST.miss_latency_hist::bucket_size 128
system.ruby.ST.miss_latency_hist::max_bucket 1279
-system.ruby.ST.miss_latency_hist::samples 862
-system.ruby.ST.miss_latency_hist::mean 591.187935
-system.ruby.ST.miss_latency_hist::gmean 580.804835
-system.ruby.ST.miss_latency_hist::stdev 98.803760
-system.ruby.ST.miss_latency_hist | 2 0.23% 0.23% | 9 1.04% 1.28% | 5 0.58% 1.86% | 97 11.25% 13.11% | 582 67.52% 80.63% | 119 13.81% 94.43% | 37 4.29% 98.72% | 11 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 862
+system.ruby.ST.miss_latency_hist::samples 854
+system.ruby.ST.miss_latency_hist::mean 595.701405
+system.ruby.ST.miss_latency_hist::gmean 585.707367
+system.ruby.ST.miss_latency_hist::stdev 95.367967
+system.ruby.ST.miss_latency_hist | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 854
system.ruby.IFETCH.latency_hist::bucket_size 128
system.ruby.IFETCH.latency_hist::max_bucket 1279
-system.ruby.IFETCH.latency_hist::samples 53
-system.ruby.IFETCH.latency_hist::mean 586.075472
-system.ruby.IFETCH.latency_hist::gmean 579.659874
-system.ruby.IFETCH.latency_hist::stdev 90.344820
-system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 53
+system.ruby.IFETCH.latency_hist::samples 50
+system.ruby.IFETCH.latency_hist::mean 623.140000
+system.ruby.IFETCH.latency_hist::gmean 615.727796
+system.ruby.IFETCH.latency_hist::stdev 99.820044
+system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.00% 10.00% | 30 60.00% 70.00% | 9 18.00% 88.00% | 6 12.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 50
+system.ruby.IFETCH.hit_latency_hist::bucket_size 64
+system.ruby.IFETCH.hit_latency_hist::max_bucket 639
+system.ruby.IFETCH.hit_latency_hist::samples 1
+system.ruby.IFETCH.hit_latency_hist::mean 537
+system.ruby.IFETCH.hit_latency_hist::gmean 537.000000
+system.ruby.IFETCH.hit_latency_hist::stdev nan
+system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 1
system.ruby.IFETCH.miss_latency_hist::bucket_size 128
system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
-system.ruby.IFETCH.miss_latency_hist::samples 53
-system.ruby.IFETCH.miss_latency_hist::mean 586.075472
-system.ruby.IFETCH.miss_latency_hist::gmean 579.659874
-system.ruby.IFETCH.miss_latency_hist::stdev 90.344820
-system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 53
+system.ruby.IFETCH.miss_latency_hist::samples 49
+system.ruby.IFETCH.miss_latency_hist::mean 624.897959
+system.ruby.IFETCH.miss_latency_hist::gmean 617.449297
+system.ruby.IFETCH.miss_latency_hist::stdev 100.069402
+system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 49
system.ruby.Directory.miss_mach_latency_hist::bucket_size 128
system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279
-system.ruby.Directory.miss_mach_latency_hist::samples 961
-system.ruby.Directory.miss_mach_latency_hist::mean 590.629553
-system.ruby.Directory.miss_mach_latency_hist::gmean 580.641121
-system.ruby.Directory.miss_mach_latency_hist::stdev 98.062205
-system.ruby.Directory.miss_mach_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.14% | 5 0.52% 1.66% | 118 12.28% 13.94% | 647 67.33% 81.27% | 126 13.11% 94.38% | 42 4.37% 98.75% | 12 1.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist::total 961
+system.ruby.Directory.miss_mach_latency_hist::samples 953
+system.ruby.Directory.miss_mach_latency_hist::mean 598.512067
+system.ruby.Directory.miss_mach_latency_hist::gmean 588.872583
+system.ruby.Directory.miss_mach_latency_hist::stdev 94.945507
+system.ruby.Directory.miss_mach_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist::total 953
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 46
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 585.413043
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 578.708439
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 94.193082
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 21.74% 21.74% | 29 63.04% 84.78% | 4 8.70% 93.48% | 2 4.35% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist::total 46
+system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 50
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 620.660000
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 616.355454
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 75.297399
+system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist::total 50
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 862
-system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 591.187935
-system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 580.804835
-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 98.803760
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 2 0.23% 0.23% | 9 1.04% 1.28% | 5 0.58% 1.86% | 97 11.25% 13.11% | 582 67.52% 80.63% | 119 13.81% 94.43% | 37 4.29% 98.72% | 11 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist::total 862
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 854
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 595.701405
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 585.707367
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 95.367967
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 854
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 53
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 586.075472
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 579.659874
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 90.344820
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 53
-system.ruby.Directory_Controller.GETX 961 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 958 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 961 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 958 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 961 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 958 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 961 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 958 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 905 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 961 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 960 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 958 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 864 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 41 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 960 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 958 0.00% 0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 624.897959
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 617.449297
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 100.069402
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49
+system.ruby.Directory_Controller.GETX 953 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 950 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 953 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 950 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 953 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 950 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 953 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 950 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 50 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 51 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 893 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 953 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 952 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 950 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 50 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 855 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 38 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 952 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 950 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 99 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 862 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 854 0.00% 0.00%
---------- End Simulation Statistics ----------
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:58:33
-gem5 started Nov 15 2015 14:58:46
-gem5 executing on ribera.cs.wisc.edu, pid 5049
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /scratch/nilay/GEM5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl
+gem5 compiled Dec 11 2015 20:23:08
+gem5 started Dec 11 2015 20:23:21
+gem5 executing on zizzer, pid 55322
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 6195134552 # Simulator tick rate (ticks/s)
-host_mem_usage 261500 # Number of bytes of host memory used
-host_seconds 16.14 # Real time elapsed on the host
+host_tick_rate 4683886556 # Simulator tick rate (ticks/s)
+host_mem_usage 202144 # Number of bytes of host memory used
+host_seconds 21.35 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:58:33
-gem5 started Nov 15 2015 14:58:46
-gem5 executing on ribera.cs.wisc.edu, pid 5048
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /scratch/nilay/GEM5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
+gem5 compiled Dec 11 2015 20:23:08
+gem5 started Dec 11 2015 20:23:21
+gem5 executing on zizzer, pid 55316
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 12448574230 # Simulator tick rate (ticks/s)
-host_mem_usage 263544 # Number of bytes of host memory used
-host_seconds 8.03 # Real time elapsed on the host
+host_tick_rate 15208030858 # Simulator tick rate (ticks/s)
+host_mem_usage 204576 # Number of bytes of host memory used
+host_seconds 6.58 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:27
-gem5 executing on ribera.cs.wisc.edu, pid 29052
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:27
+gem5 executing on zizzer, pid 26136
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2845952 # Simulator instruction rate (inst/s)
-host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1422976169 # Simulator tick rate (ticks/s)
-host_mem_usage 283520 # Number of bytes of host memory used
-host_seconds 32.29 # Real time elapsed on the host
+host_inst_rate 999914 # Simulator instruction rate (inst/s)
+host_op_rate 999914 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 499957255 # Simulator tick rate (ticks/s)
+host_mem_usage 224596 # Number of bytes of host memory used
+host_seconds 91.91 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
-system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
-system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
-system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
-system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 118400390 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91903089 # Class of executed instruction
+system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
+system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
+system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
+system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
+system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 118400390 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:30
-gem5 executing on ribera.cs.wisc.edu, pid 29102
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing
+gem5 compiled Dec 11 2015 19:54:02
+gem5 started Dec 11 2015 19:54:29
+gem5 executing on zizzer, pid 26184
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 118762761500 # Number of ticks simulated
final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 962338 # Simulator instruction rate (inst/s)
-host_op_rate 962338 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1243592305 # Simulator tick rate (ticks/s)
-host_mem_usage 296636 # Number of bytes of host memory used
-host_seconds 95.50 # Real time elapsed on the host
+host_inst_rate 510960 # Simulator instruction rate (inst/s)
+host_op_rate 510960 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 660293850 # Simulator tick rate (ticks/s)
+host_mem_usage 234860 # Number of bytes of host memory used
+host_seconds 179.86 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:25:24
-gem5 executing on ribera.cs.wisc.edu, pid 11057
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:10
+gem5 executing on zizzer, pid 11547
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic
+Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 99596491500 # Number of ticks simulated
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1150155 # Simulator instruction rate (inst/s)
-host_op_rate 1212449 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 664769571 # Simulator tick rate (ticks/s)
-host_mem_usage 303552 # Number of bytes of host memory used
-host_seconds 149.82 # Real time elapsed on the host
+host_inst_rate 676246 # Simulator instruction rate (inst/s)
+host_op_rate 712872 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 390858173 # Simulator tick rate (ticks/s)
+host_mem_usage 241720 # Number of bytes of host memory used
+host_seconds 254.82 # Real time elapsed on the host
sim_insts 172317410 # Number of instructions simulated
sim_ops 181650342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:24:37
-gem5 started Nov 15 2015 15:25:11
-gem5 executing on ribera.cs.wisc.edu, pid 11027
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing
+gem5 compiled Dec 11 2015 20:46:46
+gem5 started Dec 11 2015 20:47:11
+gem5 executing on zizzer, pid 11563
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing
+Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 230197694500 # Number of ticks simulated
final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 733775 # Simulator instruction rate (inst/s)
-host_op_rate 773584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 982953876 # Simulator tick rate (ticks/s)
-host_mem_usage 313544 # Number of bytes of host memory used
-host_seconds 234.19 # Real time elapsed on the host
+host_inst_rate 497825 # Simulator instruction rate (inst/s)
+host_op_rate 524833 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 666878578 # Simulator tick rate (ticks/s)
+host_mem_usage 251744 # Number of bytes of host memory used
+host_seconds 345.19 # Real time elapsed on the host
sim_insts 171842484 # Number of instructions simulated
sim_ops 181165371 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:22
-gem5 executing on ribera.cs.wisc.edu, pid 7765
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:42
+gem5 executing on zizzer, pid 902
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2119754 # Simulator instruction rate (inst/s)
-host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1059884256 # Simulator tick rate (ticks/s)
-host_mem_usage 284956 # Number of bytes of host memory used
-host_seconds 91.26 # Real time elapsed on the host
+host_inst_rate 1006317 # Simulator instruction rate (inst/s)
+host_op_rate 1006319 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 503162156 # Simulator tick rate (ticks/s)
+host_mem_usage 224668 # Number of bytes of host memory used
+host_seconds 192.23 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
-system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
-system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
-system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
-system.membus.trans_dist::SwapReq 22406 # Transaction distribution
-system.membus.trans_dist::SwapResp 22406 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
-system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 270179448 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445891 # number of cpu cycles simulated
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 193445773 # Class of executed instruction
+system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
+system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
+system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
+system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
+system.membus.trans_dist::SwapReq 22406 # Transaction distribution
+system.membus.trans_dist::SwapResp 22406 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
+system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 270179448 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:07:43
-gem5 started Nov 15 2015 15:08:10
-gem5 executing on ribera.cs.wisc.edu, pid 7747
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing
+gem5 compiled Dec 11 2015 20:33:09
+gem5 started Dec 11 2015 20:33:37
+gem5 executing on zizzer, pid 875
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 270599529500 # Number of ticks simulated
final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 819670 # Simulator instruction rate (inst/s)
-host_op_rate 819671 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1146593662 # Simulator tick rate (ticks/s)
-host_mem_usage 296444 # Number of bytes of host memory used
-host_seconds 236.00 # Real time elapsed on the host
+host_inst_rate 523713 # Simulator instruction rate (inst/s)
+host_op_rate 523713 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 732594560 # Simulator tick rate (ticks/s)
+host_mem_usage 234928 # Number of bytes of host memory used
+host_seconds 369.37 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:48
-gem5 executing on ribera.cs.wisc.edu, pid 9904
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:47
+gem5 executing on zizzer, pid 10151
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic
+Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 842999 # Simulator instruction rate (inst/s)
-host_op_rate 1412943 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 838671761 # Simulator tick rate (ticks/s)
-host_mem_usage 327992 # Number of bytes of host memory used
-host_seconds 156.67 # Real time elapsed on the host
+host_inst_rate 611209 # Simulator instruction rate (inst/s)
+host_op_rate 1024442 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 608071542 # Simulator tick rate (ticks/s)
+host_mem_usage 268844 # Number of bytes of host memory used
+host_seconds 216.08 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
kvmInSE=false
-Redirecting stdout to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:26
-gem5 executing on ribera.cs.wisc.edu, pid 9886
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing
+gem5 compiled Dec 11 2015 20:42:59
+gem5 started Dec 11 2015 20:43:46
+gem5 executing on zizzer, pid 10130
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 250987138500 # Number of ticks simulated
final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 528960 # Simulator instruction rate (inst/s)
-host_op_rate 886586 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1005232323 # Simulator tick rate (ticks/s)
-host_mem_usage 338112 # Number of bytes of host memory used
-host_seconds 249.68 # Real time elapsed on the host
+host_inst_rate 309334 # Simulator instruction rate (inst/s)
+host_op_rate 518472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 587856087 # Simulator tick rate (ticks/s)
+host_mem_usage 279244 # Number of bytes of host memory used
+host_seconds 426.95 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
projects / gem5.git / commitdiff