fixes to correctly simulate the vector unit

diff --git a/README b/README
index 0a1ff90723f1cf153db84c4d8616a9aee6aea674..5ba221ddc6378d1b3f72fbdfc1214f008c434682 100644 (file)
--- a/README
+++ b/README
@@ -1,7 +1,7 @@
 ==========================================================================
 RISC-V ISA Simulator
 ==========================================================================
-# Author  : Andrew Waterman
+# Author  : Andrew Waterman, Yunsup Lee
 # Date    : June 19, 2011
 # Version : (under version control)
 

diff --git a/riscv/decode.h b/riscv/decode.h
index bf16e72a0d7315f2a8fc8495a31359f2080532f4..3ef8864d496a0d852a6862535e6ffa7adc6099f5 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -152,6 +152,8 @@ public:
   }
   write_port_t<T> write_port(size_t i)
   {
+    if (zero_reg)
+      const_cast<T&>(data[0]) = 0;
     return write_port_t<T>(data[i]);
   }
   const T& operator [] (size_t i) const

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 39a9ec096568cddf2c5ba3f0613848122a68b141..e12482015b3ce436e7781f9d152df975597e6914 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -299,6 +299,8 @@ reg_t processor_t::get_pcr(int which)
       return pcr_k1;
     case PCR_VECBANK:
       return vecbanks;
+    case PCR_VECCFG:
+      return nfpr_use << 18 | nxpr_use << 12 | vl;
     case PCR_TOHOST:
       return tohost;
     case PCR_FROMHOST: