Fix different abc9 test

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index f0a9ccdb96741b67654c3feac35a240427dde2c0..55a95d8357b243f380e5d75e92fce9581af09459 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -406,13 +406,14 @@ struct XAigerWriter
                }
 
                for (auto bit : input_bits) {
+                       if (!output_bits.count(bit))
+                               continue;
                        RTLIL::Wire *wire = bit.wire;
                        // If encountering an inout port, or a keep-ed wire, then create a new wire
                        // with $inout.out suffix, make it a PO driven by the existing inout, and
                        // inherit existing inout's drivers
-                       if ((wire->port_input && wire->port_output && output_bits.count(bit) && !undriven_bits.count(bit))
+                       if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
                                        || wire->attributes.count("\\keep")) {
-                               log_assert(output_bits.count(bit));
                                RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
                                RTLIL::Wire *new_wire = module->wire(wire_name);
                                if (!new_wire)