minor review fixes

diff --git a/CHANGELOG b/CHANGELOG
index 56e5c9017174a9600e4ce029e0d9b3f428e2f9e6..bd4cd1b1b2bafe5bd699b0662b98d5e9e8212191 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -20,8 +20,10 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
       bit vectors and strings containing [01xz]*
     - Added "clkbufmap" pass
-    - Added "synth_xilinx -ise" for Spartan 6 (experimental)
-    - "synth_xilinx" now automatically inserts clock buffers
+    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
+    - Added "synth_xilinx -ise" (experimental)
+    - Added "synth_xilinx -iopad"
+    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e9e8dbfea57c017bbee052b9f8e3e0fcbc7244cf..4069094a67d3225dfca6bbfe5191a0576c8f638e 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass
                log("        (this feature is experimental and incomplete)\n");
                log("\n");
                log("    -ise\n");
-               log("        generate an output netlist suitable for ISE\n");
+               log("        generate an output netlist suitable for ISE (enables -iopad)\n");
                log("\n");
                log("    -nobram\n");
                log("        disable inference of block rams\n");