ice40_dsp: add default values for parameters

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f60e67158128c0c99e54fc1ba1c5ce47588a242a..202a43f0c6729e8ba56f846224b23a68f8761980 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
        // SB_MAC16 Input Interface
        SigSpec A = st.sigA;
-       A.extend_u0(16, st.mul->getParam(ID(A_SIGNED)).as_bool());
+       A.extend_u0(16, st.mul->connections_.at(ID(A_SIGNED), State::S0).as_bool());
        log_assert(GetSize(A) == 16);
 
        SigSpec B = st.sigB;
-       B.extend_u0(16, st.mul->getParam(ID(B_SIGNED)).as_bool());
+       B.extend_u0(16, st.mul->connections_.at(ID(B_SIGNED), State::S0).as_bool());
        log_assert(GetSize(B) == 16);
 
        SigSpec CD = st.sigCD;
@@ -248,8 +248,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
 
        cell->setParam(ID(MODE_8x8), State::S0);
-       cell->setParam(ID(A_SIGNED), st.mul->getParam(ID(A_SIGNED)).as_bool());
-       cell->setParam(ID(B_SIGNED), st.mul->getParam(ID(B_SIGNED)).as_bool());
+       cell->setParam(ID(A_SIGNED), st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
+       cell->setParam(ID(B_SIGNED), st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
 
        if (st.ffO) {
                if (st.o_lo)

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 9514e65d9aabb636689000f0c65be01c628ea2bb..fca30745384ba5bafc9abae0833dbe8e5705937d 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -63,7 +63,7 @@ code sigA sigB sigH
 endcode
 
 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
-       if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
+       if (mul->type != \SB_MAC16 || !param(mul, \A_REG, State::S0).as_bool()) {
                argQ = sigA;
                subpattern(in_dffe);
                if (dff) {
@@ -84,7 +84,7 @@ code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
 endcode
 
 code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
-       if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
+       if (mul->type != \SB_MAC16 || !param(mul, \B_REG, State::S0).as_bool()) {
                argQ = sigB;
                subpattern(in_dffe);
                if (dff) {
@@ -107,7 +107,7 @@ endcode
 code argD ffFJKG sigH clock clock_pol
        if (nusers(sigH) == 2 &&
                        (mul->type != \SB_MAC16 ||
-                        (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
+                        (!param(mul, \TOP_8x8_MULT_REG, State::S0).as_bool() && !param(mul, \BOT_8x8_MULT_REG, State::S0).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1, State::S0).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1, State::S0).as_bool()))) {
                argD = sigH;
                subpattern(out_dffe);
                if (dff) {
@@ -146,7 +146,7 @@ endcode
 
 code argD ffH sigH sigO clock clock_pol
        if (ffFJKG && nusers(sigH) == 2 &&
-                       (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
+                       (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2, State::S0).as_bool())) {
                argD = sigH;
                subpattern(out_dffe);
                if (dff) {
@@ -177,7 +177,7 @@ reject_ffH:         ;
 endcode
 
 match add
-       if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
+       if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT, State::S0).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT, State::S0).as_int() == 3)
 
        select add->type.in($add)
        choice <IdString> AB {\A, \B}
@@ -203,7 +203,7 @@ code sigCD sigO cd_signed
                if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
                        reject;
                // If accumulator, check adder width and signedness
-               if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
+               if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED, State::S0).as_bool() != param(add, \A_SIGNED).as_bool()))
                        reject;
 
                sigO = port(add, \Y);
@@ -278,7 +278,7 @@ endcode
 
 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
        if (!sigCD.empty() && sigCD != sigO &&
-                       (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
+                       (mul->type != \SB_MAC16 || (!param(mul, \C_REG, State::S0).as_bool() && !param(mul, \D_REG, State::S0).as_bool()))) {
                argQ = sigCD;
                subpattern(in_dffe);
                if (dff) {