radeonsi/gfx10: set HS/GS/CS.WGP_MODE

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index f4fabca8635e5e9873e18ca541b0cf3d75b16619..6c3509b522674670631d5e3389f42fba44adbcdd 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -191,6 +191,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
                        S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
                        S_00B848_DX10_CLAMP(1) |
                        S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
+                       S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
                        S_00B848_FLOAT_MODE(shader->config.float_mode);
 
                if (program->screen->info.chip_class < GFX10) {

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 5a3d534d475e5eb2209c4da8de27cafd31fca49a..14a3c3e036320c48b2b0e4fe5e7de8e567bb02a0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -558,6 +558,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
                                S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
                       S_00B428_DX10_CLAMP(1) |
                       S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
+                      S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
                       S_00B428_FLOAT_MODE(shader->config.float_mode) |
                       S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
 
@@ -898,6 +899,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
                        S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
                        S_00B228_DX10_CLAMP(1) |
                        S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
+                       S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
                        S_00B228_FLOAT_MODE(shader->config.float_mode) |
                        S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
                uint32_t rsrc2 =
@@ -1158,6 +1160,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
                       S_00B228_FLOAT_MODE(shader->config.float_mode) |
                       S_00B228_DX10_CLAMP(1) |
                       S_00B228_MEM_ORDERED(1) |
+                      S_00B228_WGP_MODE(1) |
                       S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
        si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
                       S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |