add SV VLIW idea

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 2004f5aaaa52b6d20c9ef887b2e5414dce416305..a06e5fc499633db4f4cc9f1215e7c6bb59569701 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2230,10 +2230,10 @@ Optional VL/MAXVL/SubVL Block:
 
 Reminder of the variable-length format from Section 1.5 of the RISC-V ISA:
 
-^ base+4 ^ base+2           ^ base             ^ number of bits             ^
-| ------ | ---------------- | ---------------- | -------------------------- |
-| ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
-| {ops}{Pred}{Reg}{VL}     || SV Prefix        |                            |
+| base+4 ..  base+2         | base             | number of bits             |
+| ------------------------- | ---------------- | -------------------------- |
+| ..xxxx   xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
+| {ops}{Pred}{Reg}{VL}      | SV Prefix        |                            |
 
 Notes: