}
}
+static VkImageAspectFlags
+sampler_aspect_from_format(enum pipe_format fmt)
+{
+ if (util_format_is_depth_or_stencil(fmt)) {
+ const struct util_format_description *desc = util_format_description(fmt);
+ if (util_format_has_depth(desc))
+ return VK_IMAGE_ASPECT_DEPTH_BIT;
+ assert(util_format_has_stencil(desc));
+ return VK_IMAGE_ASPECT_STENCIL_BIT;
+ } else
+ return VK_IMAGE_ASPECT_COLOR_BIT;
+}
+
static struct pipe_sampler_view *
zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres,
const struct pipe_sampler_view *state)
ivci.components.g = component_mapping(state->swizzle_g);
ivci.components.b = component_mapping(state->swizzle_b);
ivci.components.a = component_mapping(state->swizzle_a);
- ivci.subresourceRange.aspectMask = zink_aspect_from_format(state->format);
+
+ ivci.subresourceRange.aspectMask = sampler_aspect_from_format(state->format);
ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
return 0;
}
-VkImageAspectFlags
-zink_aspect_from_format(enum pipe_format fmt)
+static VkImageAspectFlags
+aspect_from_format(enum pipe_format fmt)
{
if (util_format_is_depth_or_stencil(fmt)) {
VkImageAspectFlags aspect = 0;
}
res->optimial_tiling = ici.tiling != VK_IMAGE_TILING_LINEAR;
- res->aspect = zink_aspect_from_format(templ->format);
+ res->aspect = aspect_from_format(templ->format);
vkGetImageMemoryRequirements(screen->dev, res->image, &reqs);
if (templ->usage == PIPE_USAGE_STAGING || (screen->winsys && (templ->bind & (PIPE_BIND_SCANOUT|PIPE_BIND_DISPLAY_TARGET|PIPE_BIND_SHARED))))