nv04: Fix build after the latest nouveau_class.h changes.
authorFrancisco Jerez <currojerez@riseup.net>
Sat, 26 Dec 2009 16:26:49 +0000 (17:26 +0100)
committerFrancisco Jerez <currojerez@riseup.net>
Mon, 28 Dec 2009 17:11:06 +0000 (18:11 +0100)
src/gallium/drivers/nv04/nv04_context.c
src/gallium/drivers/nv04/nv04_fragtex.c
src/gallium/drivers/nv04/nv04_prim_vbuf.c
src/gallium/drivers/nv04/nv04_screen.c
src/gallium/drivers/nv04/nv04_state.c
src/gallium/drivers/nv04/nv04_state_emit.c

index 4b33636b2eb5b258e474bdbd20191d7740b63153..770733a4a17be6d61b47ecfefcac4d640460abe7 100644 (file)
@@ -31,26 +31,26 @@ static boolean
 nv04_init_hwctx(struct nv04_context *nv04)
 {
        // requires a valid handle
-//     BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_NOTIFY, 1);
+//     BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_NOTIFY, 1);
 //     OUT_RING(0);
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_NOP, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_NOP, 1);
        OUT_RING(0);
 
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_CONTROL, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_CONTROL, 1);
        OUT_RING(0x40182800);
 //     OUT_RING(1<<20/*no cull*/);
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_BLEND, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_BLEND, 1);
 //     OUT_RING(0x24|(1<<6)|(1<<8));
        OUT_RING(0x120001a4);
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_FORMAT, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_FORMAT, 1);
        OUT_RING(0x332213a1);
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_FILTER, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_FILTER, 1);
        OUT_RING(0x11001010);
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_COLORKEY, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_COLORKEY, 1);
        OUT_RING(0x0);
-//     BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_OFFSET, 1);
+//     BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_OFFSET, 1);
 //     OUT_RING(SCREEN_OFFSET);
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_FOGCOLOR, 1);
        OUT_RING(0xff000000);
 
 
index 0cce71ad1de4328d6e99a5d47dc979fb8fa64618..c152b52119aae8c8f49dd353a2ff909e2b9358cf 100644 (file)
@@ -4,7 +4,7 @@
 #define _(m,tf)                                                                \
 {                                                                              \
   PIPE_FORMAT_##m,                                                             \
-  NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_##tf,                                               \
+  NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_##tf,                                               \
 }
 
 struct nv04_texture_format {
@@ -53,14 +53,14 @@ nv04_fragtex_build(struct nv04_context *nv04, int unit)
                return;
        }
 
-       nv04->fragtex.format = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER 
-               | NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER
+       nv04->fragtex.format = NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER
+               | NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER
                | nv04_fragtex_format(pt->format)
-               | ( (pt->last_level + 1) << NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT )
-               | ( log2i(pt->width0) << NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT )
-               | ( log2i(pt->height0) << NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT )
-               | NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE
-               | NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE
+               | ( (pt->last_level + 1) << NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT )
+               | ( log2i(pt->width0) << NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT )
+               | ( log2i(pt->height0) << NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT )
+               | NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE
+               | NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE
                ;
 }
 
index f6458232ae58833c1287fa429b00d4368a5224ea..25395edfd7140dbad0247c52b926b9d5a4073fe7 100644 (file)
@@ -93,7 +93,7 @@ nv04_vbuf_render_set_primitive( struct vbuf_render *render,
 
 static INLINE void nv04_2triangles(struct nv04_context* nv04, unsigned char* buffer, ushort v0, ushort v1, ushort v2, ushort v3, ushort v4, ushort v5)
 {
-       BEGIN_RING(fahrenheit,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xA),49);
+       BEGIN_RING(fahrenheit,NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0xA),49);
        OUT_RINGp(buffer + VERTEX_SIZE * v0,8);
        OUT_RINGp(buffer + VERTEX_SIZE * v1,8);
        OUT_RINGp(buffer + VERTEX_SIZE * v2,8);
@@ -105,7 +105,7 @@ static INLINE void nv04_2triangles(struct nv04_context* nv04, unsigned char* buf
 
 static INLINE void nv04_1triangle(struct nv04_context* nv04, unsigned char* buffer, ushort v0, ushort v1, ushort v2)
 {
-       BEGIN_RING(fahrenheit,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xD),25);
+       BEGIN_RING(fahrenheit,NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0xD),25);
        OUT_RINGp(buffer + VERTEX_SIZE * v0,8);
        OUT_RINGp(buffer + VERTEX_SIZE * v1,8);
        OUT_RINGp(buffer + VERTEX_SIZE * v2,8);
@@ -114,7 +114,7 @@ static INLINE void nv04_1triangle(struct nv04_context* nv04, unsigned char* buff
 
 static INLINE void nv04_1quad(struct nv04_context* nv04, unsigned char* buffer, ushort v0, ushort v1, ushort v2, ushort v3)
 {
-       BEGIN_RING(fahrenheit,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xC),33);
+       BEGIN_RING(fahrenheit,NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0xC),33);
        OUT_RINGp(buffer + VERTEX_SIZE * v0,8);
        OUT_RINGp(buffer + VERTEX_SIZE * v1,8);
        OUT_RINGp(buffer + VERTEX_SIZE * v2,8);
@@ -166,11 +166,11 @@ static void nv04_vbuf_render_tri_strip_elts(struct nv04_vbuf_render* render, con
                if (numvert<3)
                        break;
 
-               BEGIN_RING( fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0), numvert*8 );
+               BEGIN_RING( fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0), numvert*8 );
                for(j = 0; j<numvert; j++)
                        OUT_RINGp( buffer + VERTEX_SIZE * indices [i+j], 8 );
 
-               BEGIN_RING_NI( fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE(0), (numtri+1)/2 );
+               BEGIN_RING_NI( fahrenheit, NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(0), (numtri+1)/2 );
                for(j = 0; j<numtri/2; j++ )
                        OUT_RING(striptbl[j]);
                if (numtri%2)
@@ -185,7 +185,7 @@ static void nv04_vbuf_render_tri_fan_elts(struct nv04_vbuf_render* render, const
        struct nv04_context* nv04 = render->nv04;
        int i,j;
 
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0), 8);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0), 8);
        OUT_RINGp(buffer + VERTEX_SIZE * indices[0], 8);
 
        for(i = 1; i<nr_indices; i+=14)
@@ -195,12 +195,12 @@ static void nv04_vbuf_render_tri_fan_elts(struct nv04_vbuf_render* render, const
                if (numvert < 3)
                        break;
 
-               BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x1), numvert*8);
+               BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0x1), numvert*8);
 
                for(j=0;j<numvert;j++)
                        OUT_RINGp( buffer + VERTEX_SIZE * indices[ i+j ], 8 );
 
-               BEGIN_RING_NI(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE(0), (numtri+1)/2);
+               BEGIN_RING_NI(fahrenheit, NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(0), (numtri+1)/2);
                for(j = 0; j<numtri/2; j++)
                        OUT_RING(fantbl[j]);
                if (numtri%2)
index 170ce3eb7e54846b7c6f8ac856e192b909f490ee..ee9b7d2e489712144f2eed17b113b7f0f80f7a54 100644 (file)
@@ -163,10 +163,10 @@ nv04_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
                fahrenheit_class = 0;
                sub3d_class = 0;
        } else if (dev->chipset >= 0x10) {
-               fahrenheit_class = NV10_DX5_TEXTURED_TRIANGLE;
+               fahrenheit_class = NV10_TEXTURED_TRIANGLE;
                sub3d_class = NV10_CONTEXT_SURFACES_3D;
        } else {
-               fahrenheit_class=NV04_DX5_TEXTURED_TRIANGLE;
+               fahrenheit_class=NV04_TEXTURED_TRIANGLE;
                sub3d_class = NV04_CONTEXT_SURFACES_3D;
        }
 
index ef3005db5fc11e261f83dd25ee356dda8cabcd1f..e3dc4c5bf447c095663c64a22987747a88a1b749 100644 (file)
@@ -50,28 +50,28 @@ wrap_mode(unsigned wrap) {
 
        switch (wrap) {
        case PIPE_TEX_WRAP_REPEAT:
-               ret = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT;
+               ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT;
                break;
        case PIPE_TEX_WRAP_MIRROR_REPEAT:
-               ret = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT;
+               ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT;
                break;
        case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
-               ret = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE;
+               ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE;
                break;
        case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
-               ret = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER;
+               ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER;
                break;
        case PIPE_TEX_WRAP_CLAMP:
-               ret = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP;
+               ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP;
                break;
        case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
        case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
        case PIPE_TEX_WRAP_MIRROR_CLAMP:
        default:
                NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
-               ret = NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP;
+               ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP;
        }
-       return ret >> NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT;
+       return ret >> NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT;
 }
 
 static void *
@@ -84,20 +84,20 @@ nv04_sampler_state_create(struct pipe_context *pipe,
 
        ss = MALLOC(sizeof(struct nv04_sampler_state));
 
-       ss->format = ((wrap_mode(cso->wrap_s) << NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT) |
-                   (wrap_mode(cso->wrap_t) << NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT));
+       ss->format = ((wrap_mode(cso->wrap_s) << NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT) |
+                   (wrap_mode(cso->wrap_t) << NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT));
 
        if (cso->max_anisotropy > 1.0) {
-               filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE | NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE;
+               filter |= NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE | NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE;
        }
 
        switch (cso->mag_img_filter) {
        case PIPE_TEX_FILTER_LINEAR:
-               filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR;
+               filter |= NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR;
                break;
        case PIPE_TEX_FILTER_NEAREST:
        default:
-               filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST;
+               filter |= NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST;
                break;
        }
 
@@ -105,14 +105,14 @@ nv04_sampler_state_create(struct pipe_context *pipe,
        case PIPE_TEX_FILTER_LINEAR:
                switch (cso->min_mip_filter) {
                case PIPE_TEX_MIPFILTER_NEAREST:
-                       filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
+                       filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
                        break;
                case PIPE_TEX_MIPFILTER_LINEAR:
-                       filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
+                       filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
                        break;
                case PIPE_TEX_MIPFILTER_NONE:
                default:
-                       filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR;
+                       filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR;
                        break;
                }
                break;
@@ -120,14 +120,14 @@ nv04_sampler_state_create(struct pipe_context *pipe,
        default:
                switch (cso->min_mip_filter) {
                case PIPE_TEX_MIPFILTER_NEAREST:
-                       filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
+                       filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
                break;
                case PIPE_TEX_MIPFILTER_LINEAR:
-                       filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
+                       filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
                        break;
                case PIPE_TEX_MIPFILTER_NONE:
                default:
-                       filter |= NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST;
+                       filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST;
                        break;
                }
                break;
@@ -181,7 +181,7 @@ nv04_rasterizer_state_create(struct pipe_context *pipe,
         */
        rs = MALLOC(sizeof(struct nv04_rasterizer_state));
 
-       rs->blend = cso->flatshade ? NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT : NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD;
+       rs->blend = cso->flatshade ? NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT : NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD;
 
        return (void *)rs;
 }
@@ -229,16 +229,16 @@ nv04_depth_stencil_alpha_state_create(struct pipe_context *pipe,
        hw = MALLOC(sizeof(struct nv04_depth_stencil_alpha_state));
 
        hw->control = float_to_ubyte(cso->alpha.ref_value);
-       hw->control |= ( nv04_compare_func(cso->alpha.func) << NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT );
-       hw->control |= cso->alpha.enabled ? NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_TEST_ENABLE : 0;
-       hw->control |= NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ORIGIN;
-       hw->control |= cso->depth.enabled ? (1 << NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_SHIFT) : 0;
-       hw->control |= ( nv04_compare_func(cso->depth.func)<< NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT );
-       hw->control |= 1 << NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT; // no culling, handled by the draw module
-       hw->control |= NV04_DX5_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE;
-       hw->control |= NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE;
-       hw->control |= cso->depth.writemask ? (1 << NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_SHIFT) : 0;
-       hw->control |= 1 << NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT; // integer zbuffer format
+       hw->control |= ( nv04_compare_func(cso->alpha.func) << NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT );
+       hw->control |= cso->alpha.enabled ? NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE : 0;
+       hw->control |= NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN;
+       hw->control |= cso->depth.enabled ? NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE : 0;
+       hw->control |= ( nv04_compare_func(cso->depth.func)<< NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT );
+       hw->control |= 1 << NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT; // no culling, handled by the draw module
+       hw->control |= NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE;
+       hw->control |= NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE;
+       hw->control |= cso->depth.writemask ? NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE : 0;
+       hw->control |= 1 << NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT; // integer zbuffer format
 
        return (void *)hw;
 }
@@ -377,7 +377,7 @@ nv04_set_scissor_state(struct pipe_context *pipe,
 /*     struct nv04_context *nv04 = nv04_context(pipe);
 
        // XXX
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_SCISSOR_HORIZ, 2);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_SCISSOR_HORIZ, 2);
        OUT_RING  (((s->maxx - s->minx) << 16) | s->minx);
        OUT_RING  (((s->maxy - s->miny) << 16) | s->miny);*/
 }
index eb2c1c57c67dbad4b196d2618c2b8bc68df66733..bd98ae091fd95362f48825ee95e29df8a179d052 100644 (file)
@@ -58,7 +58,7 @@ static void nv04_emit_control(struct nv04_context* nv04)
 {
        uint32_t control = nv04->dsa->control;
 
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_CONTROL, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_CONTROL, 1);
        OUT_RING(control);
 }
 
@@ -75,7 +75,7 @@ static void nv04_emit_blend(struct nv04_context* nv04)
        blend|=(nv04_blend_func(nv04->blend->b_src)<<24);
        blend|=(nv04_blend_func(nv04->blend->b_dst)<<28);
 
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_BLEND, 1);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_BLEND, 1);
        OUT_RING(blend);
 }
 
@@ -84,7 +84,7 @@ static void nv04_emit_sampler(struct nv04_context *nv04, int unit)
        struct nv04_miptree *nv04mt = nv04->tex_miptree[unit];
        struct pipe_texture *pt = &nv04mt->base;
 
-       BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_OFFSET, 3);
+       BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_OFFSET, 3);
        OUT_RELOCl(nv04mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
        OUT_RELOCd(nv04mt->buffer, (nv04->fragtex.format | nv04->sampler[unit]->format), NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/);
        OUT_RING(nv04->sampler[unit]->filter);
@@ -163,7 +163,7 @@ nv04_emit_hw_state(struct nv04_context *nv04)
        if (nv04->dirty & NV04_NEW_CONTROL) {
                nv04->dirty &= ~NV04_NEW_CONTROL;
 
-               BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_CONTROL, 1);
+               BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_CONTROL, 1);
                OUT_RING(nv04->dsa->control);
        }
 
@@ -218,7 +218,7 @@ nv04_emit_hw_state(struct nv04_context *nv04)
                if (!(nv04->fp_samplers & (1 << i)))
                        continue;
                struct nv04_miptree *nv04mt = nv04->tex_miptree[i];
-               BEGIN_RING(fahrenheit, NV04_DX5_TEXTURED_TRIANGLE_OFFSET, 2);
+               BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_OFFSET, 2);
                OUT_RELOCl(nv04mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
                OUT_RELOCd(nv04mt->buffer, (nv04->fragtex.format | nv04->sampler[i]->format), NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/);
        }