(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 78fd25ce515d407b976e805280710b906a94e563..5f0a83925141b291c076a46f4e0910a49a59479f 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -45,7 +45,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 | Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
 | Rsrc2_EXTRA                  | `14:16`    | extra bits for Rsrc2 (Uses R\*_EXTRA Encoding)                            |
 | Rsrc3_EXTRA                  | `17:18`    | extra bits for Rsrc3 (Uses 2-bit R\*_EXTRA Encoding)                            |
-| MODE                          | `19:23`    | TBD                                                                       |
+| MODE                          | `19:23`    | see [[discussion]]                                                                      |
 
 ### Twin Predication (src=1, dest=1)
 
@@ -59,7 +59,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 | Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
 | MASK_SRC                     | `14:16`    | Execution Mask for Source (only on instructions with twin-predication)    |
 | ELWIDTH_SRC                  | `17:18`    | Element Width for Source (only on instructions with twin-predication)     |
-| MODE                          | `19:23`    | TBD                                                                       |
+| MODE                          | `19:23`    | see [[discussion]]                                                                       |
 
 note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added.