Gen7 has 64-bit floats but not 64-bit ints.
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
nir_lower_dsub |
nir_lower_ddiv;
- if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) {
+ if (!devinfo->has_64bit_float || (INTEL_DEBUG & DEBUG_SOFT64)) {
int64_options |= nir_lower_mov64 |
nir_lower_icmp64 |
nir_lower_iadd64 |
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
switch (inst->opcode) {
case BRW_OPCODE_MOV:
- if (!devinfo->has_64bit_types &&
+ if (!devinfo->has_64bit_float &&
+ !devinfo->has_64bit_int &&
(inst->dst.type == BRW_REGISTER_TYPE_DF ||
inst->dst.type == BRW_REGISTER_TYPE_UQ ||
inst->dst.type == BRW_REGISTER_TYPE_Q)) {
}
break;
case BRW_OPCODE_SEL:
- if (!devinfo->has_64bit_types &&
+ if (!devinfo->has_64bit_float &&
+ !devinfo->has_64bit_int &&
(inst->dst.type == BRW_REGISTER_TYPE_DF ||
inst->dst.type == BRW_REGISTER_TYPE_UQ ||
inst->dst.type == BRW_REGISTER_TYPE_Q)) {
split_virtual_grfs();
/* Lower 64 bit MOVs generated by payload lowering. */
- if (!devinfo->has_64bit_types)
+ if (!devinfo->has_64bit_float && !devinfo->has_64bit_int)
OPT(opt_algebraic);
OPT(register_coalesce);
if (type_sz(reg.type) > 4 &&
((devinfo->gen == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
- !devinfo->has_64bit_types)) {
+ !devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads two
* address register components per channel for indirectly addressed
* 64-bit sources.
table = gen4_hw_type;
}
- assert(devinfo->has_64bit_types || brw_reg_type_to_size(type) < 8 ||
- type == BRW_REGISTER_TYPE_NF);
+ assert(devinfo->gen == 11 || type != BRW_REGISTER_TYPE_NF);
+ assert(devinfo->has_64bit_float || type != BRW_REGISTER_TYPE_DF);
+ assert(devinfo->has_64bit_int ||
+ (type != BRW_REGISTER_TYPE_Q && type != BRW_REGISTER_TYPE_UQ));
if (file == BRW_IMMEDIATE_VALUE) {
assert(table[type].imm_type != (enum hw_imm_type)INVALID);
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
- if (!devinfo.has_64bit_types && type_sz(inst[i].src_type) == 8)
+ if (!devinfo.has_64bit_float &&
+ inst[i].src_type == BRW_REGISTER_TYPE_DF)
+ continue;
+
+ if (!devinfo.has_64bit_int &&
+ (inst[i].src_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].src_type == BRW_REGISTER_TYPE_UQ))
continue;
brw_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type));
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
- if (!devinfo.has_64bit_types &&
- (type_sz(inst[i].src_type) == 8 || type_sz(inst[i].dst_type) == 8)) {
+ if (!devinfo.has_64bit_float &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+ inst[i].src_type == BRW_REGISTER_TYPE_DF))
+ continue;
+
+ if (!devinfo.has_64bit_int &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+ inst[i].src_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].src_type == BRW_REGISTER_TYPE_UQ))
continue;
- }
brw_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type));
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
- if (!devinfo.has_64bit_types &&
- (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ if (!devinfo.has_64bit_float &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+ inst[i].src_type == BRW_REGISTER_TYPE_DF))
+ continue;
+
+ if (!devinfo.has_64bit_int &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+ inst[i].src_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].src_type == BRW_REGISTER_TYPE_UQ))
continue;
if (inst[i].opcode == BRW_OPCODE_MOV) {
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
- if (!devinfo.has_64bit_types &&
- (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ if (!devinfo.has_64bit_float &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+ inst[i].src_type == BRW_REGISTER_TYPE_DF))
+ continue;
+
+ if (!devinfo.has_64bit_int &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+ inst[i].src_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].src_type == BRW_REGISTER_TYPE_UQ))
continue;
if (inst[i].opcode == BRW_OPCODE_MOV) {
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
- if (!devinfo.has_64bit_types &&
- (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ if (!devinfo.has_64bit_float &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+ inst[i].src_type == BRW_REGISTER_TYPE_DF))
+ continue;
+
+ if (!devinfo.has_64bit_int &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+ inst[i].src_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].src_type == BRW_REGISTER_TYPE_UQ))
continue;
if (inst[i].opcode == BRW_OPCODE_MOV) {
clear_instructions(p);
}
- if (!devinfo.has_64bit_types)
+ if (!devinfo.has_64bit_float)
return;
/* MAC implicitly reads the accumulator */
return;
for (unsigned i = 0; i < ARRAY_SIZE(inst); i++) {
- if (!devinfo.has_64bit_types &&
- (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ if (!devinfo.has_64bit_float &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_DF ||
+ inst[i].src_type == BRW_REGISTER_TYPE_DF))
+ continue;
+
+ if (!devinfo.has_64bit_int &&
+ (inst[i].dst_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].dst_type == BRW_REGISTER_TYPE_UQ ||
+ inst[i].src_type == BRW_REGISTER_TYPE_Q ||
+ inst[i].src_type == BRW_REGISTER_TYPE_UQ))
continue;
if (inst[i].opcode == BRW_OPCODE_MOV) {
.must_use_separate_stencil = true, \
.has_llc = true, \
.has_pln = true, \
- .has_64bit_types = true, \
+ .has_64bit_float = true, \
.has_surface_tile_offset = true, \
.timestamp_frequency = 12500000
.has_sample_with_hiz = false, \
.has_pln = true, \
.has_integer_dword_mul = true, \
- .has_64bit_types = true, \
+ .has_64bit_float = true, \
+ .has_64bit_int = true, \
.supports_simd16_3src = true, \
.has_surface_tile_offset = true, \
.num_thread_per_eu = 7, \
#define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
GEN11_HW_INFO, \
- .has_64bit_types = false, \
+ .has_64bit_float = false, \
+ .has_64bit_int = false, \
.has_integer_dword_mul = false, \
.has_sample_with_hiz = false, \
.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
#define GEN12_FEATURES(_gt, _slices, _dual_subslices, _l3) \
GEN8_FEATURES, \
GEN12_HW_INFO, \
- .has_64bit_types = false, \
+ .has_64bit_float = false, \
+ .has_64bit_int = false, \
.has_integer_dword_mul = false, \
.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
.simulator_id = 22, \
bool has_llc;
bool has_pln;
- bool has_64bit_types;
+ bool has_64bit_float;
+ bool has_64bit_int;
bool has_integer_dword_mul;
bool has_compr4;
bool has_surface_tile_offset;
.shaderClipDistance = true,
.shaderCullDistance = true,
.shaderFloat64 = pdevice->info.gen >= 8 &&
- pdevice->info.has_64bit_types,
+ pdevice->info.has_64bit_float,
.shaderInt64 = pdevice->info.gen >= 8 &&
- pdevice->info.has_64bit_types,
+ pdevice->info.has_64bit_int,
.shaderInt16 = pdevice->info.gen >= 8,
.shaderResourceMinLod = pdevice->info.gen >= 9,
.variableMultisampleRate = true,