rs6000: Delete the "wu" constraint

This replaces the "wu" constraint by "v", with isa "p8v".  Or, in most
cases, use "wa", since the instructions allow all VSX registers, and it
does not change how GCC behaves, so it is clearer that way.

This also delete the unused <Fa>.

	* config/rs6000/constraints.md (define_register_constraint "wu"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wu.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wu" constraint by "v" or "wa",
	both with "p8v".
	(define_mode_attr Fa): Delete.
	* config/rs6000/vsx.md: Ditto.
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271388

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ae997cb23ff552aff5fb6c3195c3b823b2fe6a19..e9bbedb26f5485ecb09f11460625136eadb71f9b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2019-05-19  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/constraints.md (define_register_constraint "wu"):
+       Delete.
+       * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+       RS6000_CONSTRAINT_wu.
+       * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+       (rs6000_init_hard_regno_mode_ok): Adjust.
+       * config/rs6000/rs6000.md: Replace "wu" constraint by "v" or "wa",
+       both with "p8v".
+       (define_mode_attr Fa): Delete.
+       * config/rs6000/vsx.md: Ditto.
+       * doc/md.texi (Machine Constraints): Adjust.
+
 2019-05-19  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/constraints.md (define_register_constraint "wJ"):

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 38a4307c29205a7e5c8ea1da529bb82617f37eca..f9bbb7fbec030d6190db28adde99245698c041c3 100644 (file)
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -109,9 +109,6 @@
 (define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
   "VSX vector register to hold 128 bit integer or NO_REGS.")
 
-(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
-  "Altivec register to use for float/32-bit int loads/stores  or NO_REGS.")
-
 (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
   "Altivec register to use for double loads/stores  or NO_REGS.")
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1a43a8d0c2828dab8e243adcf2b5c2f6c8e5b0c2..7e2dbf98f5f4aa48bcff1fc294dead1c0b422534 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2523,7 +2523,6 @@ rs6000_debug_reg_global (void)
           "wr reg_class = %s\n"
           "ws reg_class = %s\n"
           "wt reg_class = %s\n"
-          "wu reg_class = %s\n"
           "wv reg_class = %s\n"
           "ww reg_class = %s\n"
           "wx reg_class = %s\n"
@@ -2552,7 +2551,6 @@ rs6000_debug_reg_global (void)
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
-          reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
@@ -3181,7 +3179,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
        wr - GPR if 64-bit mode is permitted.
        ws - Register class to do ISA 2.06 DF operations.
        wt - VSX register for TImode in VSX registers.
-       wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
        wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
        ww - Register class to do SF conversions in with VSX operations.
        wx - Float register if we can do 32-bit int stores.
@@ -3236,7 +3233,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
   if (TARGET_P8_VECTOR)                                                /* SFmode  */
     {
-      rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
       rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
       rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
     }

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 85dd8411d5b7a24125e03ee0f9c288cdc4461b0b..6d3056139bec8a1c65eb9ea0000f2b5ebcaad444 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1264,7 +1264,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wr,                /* GPR register if 64-bit  */
   RS6000_CONSTRAINT_ws,                /* VSX register for DF */
   RS6000_CONSTRAINT_wt,                /* VSX register for TImode */
-  RS6000_CONSTRAINT_wu,                /* Altivec register for float load/stores.  */
   RS6000_CONSTRAINT_wv,                /* Altivec register for double load/stores.  */
   RS6000_CONSTRAINT_ww,                /* FP or VSX register for vsx float ops.  */
   RS6000_CONSTRAINT_wx,                /* FPR register for STFIWX */

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b5ccb03ba4376bb4e94abd4a8511a0a8b876b24d..c5def7480d917094c9ddf43ff403e3e613f2923a 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -532,9 +532,6 @@
 ; instructions added in ISA 2.07 (power8)
 (define_mode_attr Fv2          [(SF "wy") (DF "ws") (DI "wi")])
 
-; SF/DF constraint for arithmetic on altivec registers
-(define_mode_attr Fa           [(SF "wu") (DF "wv")])
-
 ; s/d suffix for things like sdiv/ddiv
 (define_mode_attr Fs           [(SF "s")  (DF "d")])
 
@@ -834,7 +831,7 @@
 
 
 (define_insn "zero_extendsi<mode>2"
-  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wu,wj,r,wIwH")
+  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wj,r,wIwH")
        (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wIwH,wIwH")))]
   ""
   "@
@@ -846,7 +843,7 @@
    mfvsrwz %0,%x1
    xxextractuw %x0,%x1,4"
   [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")
-   (set_attr "isa" "*,*,*,*,*,*,p9v")])
+   (set_attr "isa" "*,*,*,p8v,*,*,p9v")])
 
 (define_insn_and_split "*zero_extendsi<mode>2_dot"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
@@ -1019,8 +1016,7 @@
 
 (define_insn "extendsi<mode>2"
   [(set (match_operand:EXTSI 0 "gpc_reg_operand"
-                    "=r, r,   wl,    wu,    wj,    wH,     wH,    wr")
-
+                    "=r, r,   wl,    wa,    wj,    wH,     wH,    wr")
        (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
                     "YZ, r,   Z,     Z,     r,     wH,     wH,    ?wIwH")))]
   ""
@@ -1036,7 +1032,7 @@
   [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
    (set_attr "sign_extend" "yes")
    (set_attr "length" "4,4,4,4,4,4,8,8")
-   (set_attr "isa" "*,*,*,*,*,p9v,*,*")])
+   (set_attr "isa" "*,*,*,p8v,*,p9v,*,*")])
 
 (define_split
   [(set (match_operand:EXTSI 0 "int_reg_operand")
@@ -4775,7 +4771,7 @@
 })
 
 (define_insn_and_split "*extendsfdf2_fpr"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,v")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
        (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))]
   "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
   "@
@@ -4793,7 +4789,7 @@
   DONE;
 }
   [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")
-   (set_attr "isa" "*,*,*,*,*,*,p9v")])
+   (set_attr "isa" "*,*,*,*,*,p8v,p9v")])
 
 (define_insn "*extendsfdf2_snan"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
@@ -6169,17 +6165,16 @@
 })
 
 ; An UNSPEC is used so we don't have to support SImode in FP registers.
-; The 'wu' constraint is used for the 2nd alternative to ensure stxsiwx
-; is only generated for Power8 or later.
 (define_insn "stfiwx"
   [(set (match_operand:SI 0 "memory_operand" "=Z,Z")
-       (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d,wu")]
+       (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d,wa")]
                   UNSPEC_STFIWX))]
   "TARGET_PPC_GFXOPT"
   "@
    stfiwx %1,%y0
    stxsiwx %x1,%y0"
-  [(set_attr "type" "fpstore")])
+  [(set_attr "type" "fpstore")
+   (set_attr "isa" "*,p8v")])
 
 ;; If we don't have a direct conversion to single precision, don't enable this
 ;; conversion for 32-bit without fast math, because we don't have the insn to
@@ -6372,13 +6367,14 @@
   "")
 
 (define_insn "floatunsdisf2_fcfidus"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
         (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
   "@
    fcfidus %0,%1
    xscvuxdsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 (define_insn_and_split "*floatunsdisf2_mem"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
@@ -6882,7 +6878,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand"
                "=r,         r,           r,           wI,          wH,
                 m,          Z,           Z,           r,           r,
-                r,          wIwH,        wIwH,        wIwH,        wu,
+                r,          wIwH,        wIwH,        wIwH,        v,
                 wIwH,       wH,          wH,          wIwH,        r,
                 r,          *h,          *h")
        (match_operand:SI 1 "input_operand"
@@ -6932,7 +6928,7 @@
    (set_attr "isa"
                "*,          *,           *,           *,           *,
                 *,          *,           *,           *,           *,
-                *,          *,           p9v,         p9v,         *,
+                *,          *,           p9v,         p9v,         p8v,
                 p9v,        *,           p9v,         *,           *,
                 *,          *,           *")])
 
@@ -6962,7 +6958,7 @@
                 wIwH")
        (unspec:SI [(match_operand:SF 1 "input_operand"
                "r,          m,           Z,           Z,        r,
-                f,          v,           wu,          wIwH,     wIwH,
+                f,          v,           wa,          wIwH,     wIwH,
                 r")]
                    UNSPEC_SI_FROM_SF))
    (clobber (match_scratch:V4SF 2
@@ -7009,7 +7005,7 @@
                 4")
    (set_attr "isa"
                "*,          *,           *,           *,        *,
-                *,          p9v,         *,           *,        *,
+                *,          p9v,         p8v,         *,        *,
                 *")])
 
 ;; movsi_from_sf with zero extension
@@ -7295,12 +7291,12 @@
 
 (define_insn "movsf_hardfloat"
   [(set (match_operand:SF 0 "nonimmediate_operand"
-        "=!r,       f,         v,          wu,        m,         wY,
+        "=!r,       f,         v,          wa,        m,         wY,
          Z,         m,         ww,         !r,        f,         ww,
          !r,        *c*l,      !r,         *h")
        (match_operand:SF 1 "input_operand"
         "m,         m,         wY,         Z,         f,         v,
-         wu,        r,         j,          j,         f,         ww,
+         wa,        r,         j,          j,         f,         ww,
          r,         r,         *h,         0"))]
   "(register_operand (operands[0], SFmode)
    || register_operand (operands[1], SFmode))
@@ -7329,8 +7325,8 @@
         fpstore,    store,     veclogical, integer,   fpsimple,  fpsimple,
         *,          mtjmpr,    mfjmpr,     *")
    (set_attr "isa"
-       "*,          *,         p9v,        *,         *,         p9v,
-        *,          *,         *,          *,         *,         *,
+       "*,          *,         p9v,        p8v,       *,         p9v,
+        p8v,        *,         *,          *,         *,         *,
         *,          *,         *,          *")])
 
 ;;     LWZ          LFIWZX     STW        STFIWX     MTVSRWZ    MFVSRWZ
@@ -7413,11 +7409,11 @@
 ;;         STXSIWX      GPR->VSX   VSX->GPR   GPR->GPR
 (define_insn_and_split "movsf_from_si"
   [(set (match_operand:SF 0 "nonimmediate_operand"
-           "=!r,       f,         v,         wu,        m,         Z,
+           "=!r,       f,         v,         wa,        m,         Z,
             Z,         wy,        ?r,        !r")
        (unspec:SF [(match_operand:SI 1 "input_operand" 
            "m,         m,         wY,        Z,         r,         f,
-            wu,        r,         wy,        r")]
+            wa,        r,         wy,        r")]
                   UNSPEC_SF_FROM_SI))
    (clobber (match_scratch:DI 2
            "=X,        X,         X,         X,         X,         X,
@@ -7460,8 +7456,8 @@
            "load,       fpload,    fpload,    fpload,    store,     fpstore,
             fpstore,    vecfloat,  mffgpr,    *")
    (set_attr "isa"
-           "*,          *,         p9v,       *,         *,         *,
-            *,          *,         *,         *")])
+           "*,          *,         p9v,       p8v,       *,         *,
+            p8v,        *,         *,         *")])
 
 \f
 ;; Move 64-bit binary/decimal floating point

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index b96d24eb1538df69a6a392888ccb0bc20cb529cb..fd92704b3c47e5e4447e3538d80d11f7d7a1022a 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3199,7 +3199,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS.
 When using any of the register constraints (@code{wa}, @code{wd},
 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
 @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
-@code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
+@code{wt}, @code{wv}, @code{ww}, or @code{wy})
 that take VSX registers, you must use @code{%x<n>} in the template so
 that the correct register is used.  Otherwise the register number
 output in the assembly file will be incorrect if an Altivec register
@@ -3295,9 +3295,6 @@ VSX vector register to hold scalar double values or NO_REGS.
 @item wt
 VSX vector register to hold 128 bit integer or NO_REGS.
 
-@item wu
-Altivec register to use for float/32-bit int loads/stores  or NO_REGS.
-
 @item wv
 Altivec register to use for double loads/stores  or NO_REGS.