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freedreno/a6xx: fix shaders w/ >= 24 regs
authorRob Clark <robdclark@gmail.com>
Wed, 12 Sep 2018 19:54:47 +0000 (15:54 -0400)
committerRob Clark <robdclark@gmail.com>
Thu, 27 Sep 2018 19:49:14 +0000 (15:49 -0400)
Possibly these bits mean something else now.  Blob always seems to use
FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads
to overlap registers.

Signed-off-by: Rob Clark <robdclark@gmail.com>
src/gallium/drivers/freedreno/a6xx/fd6_program.c patch | blob | history

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index b2354de7e30f960a539b04d33ed00692c079c914..6ce02d632104453c13392a727c0bc63830438349 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -310,7 +310,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
        setup_stages(emit, s);
 
-       fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
+       fssz = FOUR_QUADS;
 
        pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
        psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);