enum vc4_bo_mode mode;
};
-struct exec_info {
+struct vc4_exec_info {
+ /* Sequence number for this bin/render job. */
+ uint64_t seqno;
+
/* Kernel-space copy of the ioctl arguments */
struct drm_vc4_submit_cl *args;
void *unvalidated,
uint32_t len,
bool is_bin,
- struct exec_info *exec);
+ struct vc4_exec_info *exec);
int
-vc4_validate_shader_recs(struct drm_device *dev, struct exec_info *exec);
+vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
struct vc4_validated_shader_info *
-vc4_validate_shader(struct drm_gem_cma_object *shader_obj,
- uint32_t start_offset);
+vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
#endif /* VC4_DRV_H */
#include "vc4_drv.h"
int
-vc4_cl_validate(struct drm_device *dev, struct exec_info *exec)
+vc4_cl_validate(struct drm_device *dev, struct vc4_exec_info *exec)
{
struct drm_vc4_submit_cl *args = exec->args;
void *temp = NULL;
exec->shader_state = temp + exec_size;
exec->shader_state_size = args->shader_rec_count;
- ret = copy_from_user(bin, args->bin_cl, args->bin_cl_size);
+ ret = copy_from_user(bin,
+ (void __user *)(uintptr_t)args->bin_cl,
+ args->bin_cl_size);
if (ret) {
DRM_ERROR("Failed to copy in bin cl\n");
goto fail;
}
- ret = copy_from_user(render, args->render_cl, args->render_cl_size);
+ ret = copy_from_user(render,
+ (void __user *)(uintptr_t)args->render_cl,
+ args->render_cl_size);
if (ret) {
DRM_ERROR("Failed to copy in render cl\n");
goto fail;
}
- ret = copy_from_user(exec->shader_rec_u, args->shader_rec,
+ ret = copy_from_user(exec->shader_rec_u,
+ (void __user *)(uintptr_t)args->shader_rec,
args->shader_rec_size);
if (ret) {
DRM_ERROR("Failed to copy in shader recs\n");
goto fail;
}
- ret = copy_from_user(exec->uniforms_u, args->uniforms,
+ ret = copy_from_user(exec->uniforms_u,
+ (void __user *)(uintptr_t)args->uniforms,
args->uniforms_size);
if (ret) {
DRM_ERROR("Failed to copy in uniforms cl\n");
#include "vc4_packet.h"
#define VALIDATE_ARGS \
- struct exec_info *exec, \
+ struct vc4_exec_info *exec, \
void *validated, \
void *untrusted
}
static bool
-vc4_use_bo(struct exec_info *exec,
+vc4_use_bo(struct vc4_exec_info *exec,
uint32_t hindex,
enum vc4_bo_mode mode,
struct drm_gem_cma_object **obj)
}
static bool
-vc4_use_handle(struct exec_info *exec,
+vc4_use_handle(struct vc4_exec_info *exec,
uint32_t gem_handles_packet_index,
enum vc4_bo_mode mode,
struct drm_gem_cma_object **obj)
}
static bool
-check_tex_size(struct exec_info *exec, struct drm_gem_cma_object *fbo,
+check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
uint32_t offset, uint8_t tiling_format,
uint32_t width, uint32_t height, uint8_t cpp)
{
bool render;
uint16_t len;
const char *name;
- int (*func)(struct exec_info *exec, void *validated, void *untrusted);
+ int (*func)(struct vc4_exec_info *exec, void *validated,
+ void *untrusted);
} cmd_info[] = {
[VC4_PACKET_HALT] = { 1, 1, 1, "halt", NULL },
[VC4_PACKET_NOP] = { 1, 1, 1, "nop", NULL },
void *unvalidated,
uint32_t len,
bool is_bin,
- struct exec_info *exec)
+ struct vc4_exec_info *exec)
{
uint32_t dst_offset = 0;
uint32_t src_offset = 0;
}
static bool
-reloc_tex(struct exec_info *exec,
+reloc_tex(struct vc4_exec_info *exec,
void *uniform_data_u,
struct vc4_texture_sample_info *sample,
uint32_t texture_handle_index)
static int
validate_shader_rec(struct drm_device *dev,
- struct exec_info *exec,
+ struct vc4_exec_info *exec,
struct vc4_shader_state *state)
{
uint32_t *src_handles;
switch (relocs[i].type) {
case RELOC_CODE:
+ if (src_offset != 0) {
+ DRM_ERROR("Shaders must be at offset 0 of "
+ "the BO.\n");
+ goto fail;
+ }
+
kfree(validated_shader);
- validated_shader = vc4_validate_shader(bo[i],
- src_offset);
+ validated_shader = vc4_validate_shader(bo[i]);
if (!validated_shader)
goto fail;
int
vc4_validate_shader_recs(struct drm_device *dev,
- struct exec_info *exec)
+ struct vc4_exec_info *exec)
{
uint32_t i;
int ret = 0;
}
struct vc4_validated_shader_info *
-vc4_validate_shader(struct drm_gem_cma_object *shader_obj,
- uint32_t start_offset)
+vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
{
bool found_shader_end = false;
int shader_end_ip = 0;
for (i = 0; i < ARRAY_SIZE(validation_state.live_clamp_offsets); i++)
validation_state.live_clamp_offsets[i] = ~0;
- if (start_offset + sizeof(uint64_t) > shader_obj->base.size) {
- DRM_ERROR("shader starting at %d outside of BO sized %d\n",
- start_offset,
- shader_obj->base.size);
- return NULL;
- }
- shader = shader_obj->vaddr + start_offset;
- max_ip = (shader_obj->base.size - start_offset) / sizeof(uint64_t);
+ shader = shader_obj->vaddr;
+ max_ip = shader_obj->base.size / sizeof(uint64_t);
validated_shader = kcalloc(sizeof(*validated_shader), 1, GFP_KERNEL);
if (!validated_shader)
}
if (ip == max_ip) {
- DRM_ERROR("shader starting at %d failed to terminate before "
+ DRM_ERROR("shader failed to terminate before "
"shader BO end at %d\n",
- start_offset,
shader_obj->base.size);
goto fail;
}
struct drm_vc4_submit_cl submit;
memset(&submit, 0, sizeof(submit));
- submit.bo_handles = vc4->bo_handles.base;
+ submit.bo_handles = (uintptr_t)vc4->bo_handles.base;
submit.bo_handle_count = (vc4->bo_handles.next -
vc4->bo_handles.base) / 4;
- submit.bin_cl = vc4->bcl.base;
+ submit.bin_cl = (uintptr_t)vc4->bcl.base;
submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
- submit.render_cl = vc4->rcl.base;
+ submit.render_cl = (uintptr_t)vc4->rcl.base;
submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
- submit.shader_rec = vc4->shader_rec.base;
+ submit.shader_rec = (uintptr_t)vc4->shader_rec.base;
submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
submit.shader_rec_count = vc4->shader_rec_count;
- submit.uniforms = vc4->uniforms.base;
+ submit.uniforms = (uintptr_t)vc4->uniforms.base;
submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
if (!(vc4_debug & VC4_DEBUG_NORAST)) {
/*
- * Copyright © 2014 Broadcom
+ * Copyright © 2014-2015 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
#define DRM_VC4_SUBMIT_CL 0x00
#define DRM_VC4_WAIT_SEQNO 0x01
#define DRM_VC4_WAIT_BO 0x02
+#define DRM_VC4_CREATE_BO 0x03
+#define DRM_VC4_MMAP_BO 0x04
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
+#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
/**
* then writes out the state updates and draw calls necessary per tile
* to the tile allocation BO.
*/
- void __user *bin_cl;
+ uint64_t bin_cl;
/* Pointer to the render command list.
*
* stored rendering for that tile, then store the tile's state back to
* memory.
*/
- void __user *render_cl;
+ uint64_t render_cl;
/* Pointer to the shader records.
*
* and an attribute count), so those BO indices into bo_handles are
* just stored as uint32_ts before each shader record passed in.
*/
- void __user *shader_rec;
+ uint64_t shader_rec;
/* Pointer to uniform data and texture handles for the textures
* referenced by the shader.
* because the kernel has to determine the sizes anyway during shader
* code validation.
*/
- void __user *uniforms;
- void __user *bo_handles;
+ uint64_t uniforms;
+ uint64_t bo_handles;
/* Size in bytes of the binner command list. */
uint32_t bin_cl_size;
/* Number of BO handles passed in (size is that times 4). */
uint32_t bo_handle_count;
+ uint32_t flags;
uint32_t pad;
/* Returned value of the seqno of this render job (for the
uint64_t timeout_ns;
};
+/**
+ * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
+ *
+ * There are currently no values for the flags argument, but it may be
+ * used in a future extension.
+ */
+struct drm_vc4_create_bo {
+ uint32_t size;
+ uint32_t flags;
+ /** Returned GEM handle for the BO. */
+ uint32_t handle;
+ uint32_t pad;
+};
+
+/**
+ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
+ *
+ * This doesn't actually perform an mmap. Instead, it returns the
+ * offset you need to use in an mmap on the DRM device node. This
+ * means that tools like valgrind end up knowing about the mapped
+ * memory.
+ *
+ * There are currently no values for the flags argument, but it may be
+ * used in a future extension.
+ */
+struct drm_vc4_mmap_bo {
+ /** Handle for the object being mapped. */
+ uint32_t handle;
+ uint32_t flags;
+ /** offset into the drm node to use for subsequent mmap call. */
+ uint64_t offset;
+};
+
#endif /* _UAPI_VC4_DRM_H_ */
}
static int
-vc4_simulator_pin_bos(struct drm_device *dev, struct exec_info *exec)
+vc4_simulator_pin_bos(struct drm_device *dev, struct vc4_exec_info *exec)
{
struct drm_vc4_submit_cl *args = exec->args;
struct vc4_context *vc4 = dev->vc4;
}
static int
-vc4_simulator_unpin_bos(struct exec_info *exec)
+vc4_simulator_unpin_bos(struct vc4_exec_info *exec)
{
for (int i = 0; i < exec->bo_count; i++) {
struct drm_gem_cma_object *obj = exec->bo[i].bo;
uint32_t winsys_stride = ctex ? ctex->bo->simulator_winsys_stride : 0;
uint32_t sim_stride = ctex ? ctex->slices[0].stride : 0;
uint32_t row_len = MIN2(sim_stride, winsys_stride);
- struct exec_info exec;
+ struct vc4_exec_info exec;
struct drm_device local_dev = {
.vc4 = vc4,
.simulator_mem_next = OVERFLOW_SIZE,
#include "vc4_context.h"
#include "vc4_qpu_defines.h"
-struct exec_info;
+struct vc4_exec_info;
#define DRM_INFO(...) fprintf(stderr, __VA_ARGS__)
#define DRM_ERROR(...) fprintf(stderr, __VA_ARGS__)
drm_gem_cma_create(struct drm_device *dev, size_t size);
int
-vc4_cl_validate(struct drm_device *dev, struct exec_info *exec);
+vc4_cl_validate(struct drm_device *dev, struct vc4_exec_info *exec);
#endif /* VC4_SIMULATOR_VALIDATE_H */
projects / mesa.git / commitdiff