mem: Change AbstractMemory defaults to match the common case

This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.

diff --git a/configs/example/fs.py b/configs/example/fs.py
index ff59ca67d33bbf64ff89f5ac8e29880e9cdb5b97..bcd58ca5ef1cf7b80038aecbbe5e99c90f7a9222 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -174,8 +174,7 @@ CacheConfig.config_cache(options, test_sys)
 
 # Create the appropriate memory controllers and connect them to the
 # memory bus
-test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
-                      for r in test_sys.mem_ranges]
+test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
 for i in xrange(len(test_sys.mem_ctrls)):
     test_sys.mem_ctrls[i].port = test_sys.membus.master
 
@@ -225,7 +224,7 @@ if len(bm) == 2:
 
     # Create the appropriate memory controllers and connect them to the
     # memory bus
-    drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
+    drive_sys.mem_ctrls = [DriveMemClass(range = r)
                            for r in drive_sys.mem_ranges]
     for i in xrange(len(drive_sys.mem_ctrls)):
         drive_sys.mem_ctrls[i].port = drive_sys.membus.master

diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index a254841d221710098de45517332dffa10f38aef6..60c4be2b322cba28366e9a6df46b67964774f726 100644 (file)
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -128,9 +128,7 @@ for (i, cpu) in enumerate(system.cpu):
 
 # Create the appropriate memory controllers and connect them to the
 # PIO bus
-system.mem_ctrls = [TestMemClass(range = r,
-                                 conf_table_reported = True)
-                    for r in system.mem_ranges]
+system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
 for i in xrange(len(system.physmem)):
     system.mem_ctrls[i].port = system.piobus.master
 

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 731e8abe761ce5a76baec9520d6d0bf49dc6113d..167108850ec6aacfa8419f314b2293c6df62d0e3 100644 (file)
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -159,8 +159,8 @@ class RealView(Platform):
     max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
 
     def setupBootLoader(self, mem_bus, cur_sys, loc):
-        self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'),
-                                                    size = '64MB'))
+        self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
+                                  conf_table_reported = False)
         self.nvmem.port = mem_bus.master
         cur_sys.boot_loader = loc('boot.arm')
 
@@ -357,7 +357,8 @@ class VExpress_EMM(RealView):
                         InterruptLine=2, InterruptPin=2)
 
 
-    vram           = SimpleMemory(range = AddrRange(0x18000000, size='32MB'))
+    vram           = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
+                                  conf_table_reported = False)
     rtc            = PL031(pio_addr=0x1C170000, int_num=36)
 
     l2x0_fake      = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
@@ -372,7 +373,8 @@ class VExpress_EMM(RealView):
     mmc_fake       = AmbaFake(pio_addr=0x1c050000)
 
     def setupBootLoader(self, mem_bus, cur_sys, loc):
-        self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
+        self.nvmem = SimpleMemory(range = AddrRange('64MB'),
+                                  conf_table_reported = False)
         self.nvmem.port = mem_bus.master
         cur_sys.boot_loader = loc('boot_emm.arm')
         cur_sys.atags_addr = 0x80000100

diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 22a4a18930f65c035470cb1d62ec7e80cb3574b2..ab1a6028c587f2f14430db772d64dae00e4c41e5 100644 (file)
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -46,7 +46,10 @@ class AbstractMemory(MemObject):
     type = 'AbstractMemory'
     abstract = True
     cxx_header = "mem/abstract_mem.hh"
-    range = Param.AddrRange(AddrRange('128MB'), "Address range")
+
+    # A default memory size of 128 MB (starting at 0) is used to
+    # simplify the regressions
+    range = Param.AddrRange('128MB', "Address range (potentially interleaved)")
     null = Param.Bool(False, "Do not store data, always return zero")
 
     # All memories are passed to the global physical memory, and
@@ -57,4 +60,4 @@ class AbstractMemory(MemObject):
     # Should the bootloader include this memory when passing
     # configuration information about the physical memory layout to
     # the kernel, e.g. using ATAG or ACPI
-    conf_table_reported = Param.Bool(False, "Report to configuration table")
+    conf_table_reported = Param.Bool(True, "Report to configuration table")

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 9a0eb9395969e32b34f3fb0dd57a2e4876eb551c..e9487546d9c03c168b525c2b3aa3f7d65576368b 100644 (file)
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -228,8 +228,7 @@ class BaseFSSystem(BaseSystem):
 
         # create the memory controllers and connect them, stick with
         # the physmem name to avoid bumping all the reference stats
-        system.physmem = [self.mem_class(range = r,
-                                         conf_table_reported = True)
+        system.physmem = [self.mem_class(range = r)
                           for r in system.mem_ranges]
         for i in xrange(len(system.physmem)):
             system.physmem[i].port = system.membus.master

diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index fcbfd6b7fc17efc976967ec5bce1ac220ff7c60f..57f9b6679aa676bc4211faf4c0ec032a13940af9 100644 (file)
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -89,8 +89,7 @@ for (i, cpu) in enumerate(system.cpu):
     # Set access_phys_mem to True for ruby port
     system.ruby._cpu_ruby_ports[i].access_phys_mem = True
 
-system.physmem = [DDR3_1600_x64(range = r,
-                                conf_table_reported = True)
+system.physmem = [DDR3_1600_x64(range = r)
                   for r in system.mem_ranges]
 for i in xrange(len(system.physmem)):
     system.physmem[i].port = system.piobus.master

diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 68bf048b68f938ca28856ca88a31513c86398559..96357f40c7cbf32ad0ab90f0768c9e05769fd1d3 100644 (file)
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -45,8 +45,7 @@ cpu.connectAllPorts(system.membus)
 
 # create the memory controllers and connect them, stick with
 # the physmem name to avoid bumping all the reference stats
-system.physmem = [SimpleMemory(range = r,
-                               conf_table_reported = True)
+system.physmem = [SimpleMemory(range = r)
                   for r in system.mem_ranges]
 for i in xrange(len(system.physmem)):
     system.physmem[i].port = system.membus.master