litescope: pep8 (E203)

diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py
index 839682559157b2799fea0807d00bb13a1b6b62a8..2a494147c3f7d83db1272662587183a850aa1af3 100644 (file)
--- a/misoclib/tools/litescope/bridge/uart2wb.py
+++ b/misoclib/tools/litescope/bridge/uart2wb.py
@@ -47,8 +47,8 @@ class UARTMux(Module):
 
 class LiteScopeUART2WB(Module, AutoCSR):
     cmds = {
-        "write"    : 0x01,
-        "read"    : 0x02
+        "write": 0x01,
+        "read": 0x02
     }
     def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False):
         self.wishbone = wishbone.Interface()

diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py
index 9a0b65bbdbe930f75a2f30232ec2d1b630be8dad..877e7bf2f15bfff3c82f001153a29219fd787974 100644 (file)
--- a/misoclib/tools/litescope/host/driver/uart.py
+++ b/misoclib/tools/litescope/host/driver/uart.py
@@ -9,8 +9,8 @@ def write_b(uart, data):
 
 class LiteScopeUARTDriver:
     cmds = {
-        "write"    : 0x01,
-        "read"    : 0x02
+        "write": 0x01,
+        "read": 0x02
     }
     def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
         self.port = port

diff --git a/misoclib/tools/litescope/host/dump/__init__.py b/misoclib/tools/litescope/host/dump/__init__.py
index 2b562ae02d5fbe83db9407f704faaf159fd1708d..84a9896e382fb912e0fdcd3d20d06b1643a7a2fe 100644 (file)
--- a/misoclib/tools/litescope/host/dump/__init__.py
+++ b/misoclib/tools/litescope/host/dump/__init__.py
@@ -77,7 +77,7 @@ class Var:
 
     def change(self, cnt):
         r = ""
-        try :
+        try:
             if self.values[cnt+1] != self.val:
                 r += "b"
                 r += dec2bin(self.values[cnt+1], self.width)
@@ -85,7 +85,7 @@ class Var:
                 r += self.vcd_id
                 r += "\n"
                 return r
-        except :
+        except:
             return r
         return r