rename fmv[ft]g*/fcvt[ft]g* to m[tf]fpr*/c[tf]fpr*

diff --git a/openpower/isa/fpcvt.mdwn b/openpower/isa/fpcvt.mdwn
index 097f973f32d67c34cc55f3ff14e465df7b1038f2..bd7b0688c1057fcd56931a70a8417479d997f8f5 100644 (file)
--- a/openpower/isa/fpcvt.mdwn
+++ b/openpower/isa/fpcvt.mdwn
@@ -23,8 +23,8 @@ Special Registers Altered:
 
 X-Form
 
-* fcvtfg FRT,RB,IT (Rc=0)
-* fcvtfg. FRT,RB,IT (Rc=1)
+* ctfpr FRT,RB,IT (Rc=0)
+* ctfpr. FRT,RB,IT (Rc=1)
 
 Pseudo-code:
 
@@ -66,8 +66,8 @@ Special Registers Altered:
 
 X-Form
 
-* fcvtfgs FRT,RB,IT (Rc=0)
-* fcvtfgs. FRT,RB,IT (Rc=1)
+* ctfprs FRT,RB,IT (Rc=0)
+* ctfprs. FRT,RB,IT (Rc=1)
 
 Pseudo-code:
 
@@ -103,10 +103,10 @@ Special Registers Altered:
 
 XO-Form
 
-* fcvttg RT,FRB,CVM,IT (OE=0 Rc=0)
-* fcvttg. RT,FRB,CVM,IT (OE=0 Rc=1)
-* fcvttgo RT,FRB,CVM,IT (OE=1 Rc=0)
-* fcvttgo. RT,FRB,CVM,IT (OE=1 Rc=1)
+* cffpr RT,FRB,CVM,IT (OE=0 Rc=0)
+* cffpr. RT,FRB,CVM,IT (OE=0 Rc=1)
+* cffpro RT,FRB,CVM,IT (OE=1 Rc=0)
+* cffpro. RT,FRB,CVM,IT (OE=1 Rc=1)
 
 Pseudo-code:
 

diff --git a/openpower/isa/fpmove.mdwn b/openpower/isa/fpmove.mdwn
index 09b55c53a6b3f713321aa1cec3dbaf20b87beffa..cc628294e9dbf3a8cfba31a8ac88a94b0f4ea962 100644 (file)
--- a/openpower/isa/fpmove.mdwn
+++ b/openpower/isa/fpmove.mdwn
@@ -81,8 +81,8 @@ Special Registers Altered:
 
 X-Form
 
-* fmvtg RT,FRB (Rc=0)
-* fmvtg. RT,FRB (Rc=1)
+* mffpr RT,FRB (Rc=0)
+* mffpr. RT,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -96,8 +96,8 @@ Special Registers Altered:
 
 X-Form
 
-* fmvtgs RT,FRB (Rc=0)
-* fmvtgs. RT,FRB (Rc=1)
+* mffprs RT,FRB (Rc=0)
+* mffprs. RT,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -111,7 +111,7 @@ Special Registers Altered:
 
 X-Form
 
-* fmvfg FRT,RB
+* mtfpr FRT,RB
 
 Pseudo-code:
 
@@ -125,7 +125,7 @@ Special Registers Altered:
 
 X-Form
 
-* fmvfgs FRT,RB
+* mtfprs FRT,RB
 
 Pseudo-code:
 

diff --git a/openpower/isafunctions/bfp.mdwn b/openpower/isafunctions/bfp.mdwn
index 2e89804b6de89707caeb1fc858634c7a14b2de5a..52df886308439a1afe554834058dab610fadc3bf 100644 (file)
--- a/openpower/isafunctions/bfp.mdwn
+++ b/openpower/isafunctions/bfp.mdwn
@@ -1,6 +1,6 @@
 # binary-floating-point helper functions
 
-`bfp_*` and related functions as needed by fcvt* from PowerISA v3.1B Book I
+`bfp_*` and related functions as needed by c[ft]fpr* from PowerISA v3.1B Book I
 section 7.6.2.2
 
     def reset_xflags():

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index 0d4c25f807f62e1927dac3e9bfe954df956cedb1..a251c8ea9f8c654fa8c3d621ea7e9653270d46c6 100644 (file)
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -15,8 +15,8 @@ mfspr,NORMAL,,2P,EXTRA3,EN,d:RS,s:SPR,0,0,SPR,0,0,RT,0,0,0
 popcntw,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 mtspr,NORMAL,,2P,EXTRA3,EN,d:SPR,s:RS,0,0,RS,0,0,SPR,0,0,0
 popcntd,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-fmvfgs,NORMAL,,2P,EXTRA3,EN,d:FRT,s:RB,0,0,0,RB,0,FRT,0,0,0
-fmvfg,NORMAL,,2P,EXTRA3,EN,d:FRT,s:RB,0,0,0,RB,0,FRT,0,0,0
+mtfprs,NORMAL,,2P,EXTRA3,EN,d:FRT,s:RB,0,0,0,RB,0,FRT,0,0,0
+mtfpr,NORMAL,,2P,EXTRA3,EN,d:FRT,s:RB,0,0,0,RB,0,FRT,0,0,0
 addic,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
 addi,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 addis,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
@@ -66,7 +66,7 @@ facoshs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fatanhs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fexp2m1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flog2p1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fcvtfgs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0
+ctfprs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0
 fexpm1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flogp1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fexp10m1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
@@ -74,7 +74,7 @@ flog10p1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fcfids,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fexp2s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flog2s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fmvtgs,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
+mffprs,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
 fexps,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flogs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fexp10s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
@@ -92,7 +92,7 @@ frsqrte,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 4/14=fctiwu,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 4/15=fctiwuz,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 8/8=fabs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fcvttg,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
+cffpr,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
 12/8=frin,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 13/8=friz,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 14/8=frip,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
@@ -121,8 +121,8 @@ facosh,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fatanh,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fexp2m1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flog2p1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fcvttgo,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
-fcvtfg,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0
+cffpro,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
+ctfpr,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0
 fexpm1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flogp1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 25/14=fctid,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
@@ -132,7 +132,7 @@ flog10p1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 26/14=fcfid,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 fexp2,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flog2,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fmvtg,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
+mffpr,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
 fexp,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 flog,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
 29/14=fctidu,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0

diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
index 5dd238c8e5899da5500922022f360cfa3e4f6792..e9d307c4af33817bae7ef1121b282d3daeef8b2a 100644 (file)
--- a/openpower/isatables/minor_59.csv
+++ b/openpower/isatables/minor_59.csv
@@ -80,6 +80,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 # 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmods,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainders,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mffprs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ctfprs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtfprs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/openpower/isatables/minor_63.csv b/openpower/isatables/minor_63.csv
index c5d8a4c6ce1bc6693085a03daf47b67d8b3796f8..6f1252416e3728c9b54c8eb41822d787bdd2ea34 100644 (file)
--- a/openpower/isatables/minor_63.csv
+++ b/openpower/isatables/minor_63.csv
@@ -105,8 +105,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 # 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmod,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainder,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttg,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgo,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cffpr,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cffpro,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mffpr,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ctfpr,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtfpr,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 8ad794c5a65032a22d8f476853a25f95ffd6f9c3..3f3e62e19812307e7fc3fa4422e37577fae83ef6 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1963,10 +1963,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
                        "dsld", "dsrd", "maddedus",
                        "sadd", "saddw", "sadduw",
-                       "fcvttg", "fcvttgo",
-                       "fmvtg", "fmvtgs",
-                       "fcvtfg", "fcvtfgs",
-                       "fmvfg", "fmvfgs",
+                       "cffpr", "cffpro",
+                       "mffpr", "mffprs",
+                       "ctfpr", "ctfprs",
+                       "mtfpr", "mtfprs",
                        "maddsubrs", "maddrs"
                        ]:
             illegal = False

diff --git a/src/openpower/decoder/isa/test_caller_fmv_fcvt.py b/src/openpower/decoder/isa/test_caller_fmv_fcvt.py
index 3e9233f3b5123ef04efcaab6c61af17e9cc3a393..3452df46f6be541cc701a4a127b2dc739fa81d68 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fmv_fcvt.py
+++ b/src/openpower/decoder/isa/test_caller_fmv_fcvt.py
@@ -1,4 +1,4 @@
-""" fmv/fcvt tests
+""" [mc][ft]fpr* tests
 """
 
 import unittest

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index fb90b135d23c1bec0cbbdfaf42f238de4718aed4..707e3986fb5778b198241ee99040c8086c92cf3e 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -783,10 +783,10 @@ _insns = [
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
     "fmvis",                                            # FP load immediate
     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
-    "fcvttg", "fcvttgo",
-    "fmvtg", "fmvtgs",
-    "fcvtfg", "fcvtfgs",
-    "fmvfg", "fmvfgs",
+    "cffpr", "cffpro",
+    "mffpr", "mffprs",
+    "ctfpr", "ctfprs",
+    "mtfpr", "mtfprs",
     'grev', 'grev.', 'grevi', 'grevi.',
     'grevw', 'grevw.', 'grevwi', 'grevwi.',
     "hrfid", "icbi", "icbt", "isel", "isync",

diff --git a/src/openpower/test/fmv_fcvt/fmv_fcvt.py b/src/openpower/test/fmv_fcvt/fmv_fcvt.py
index 53909edb6aca947b3778baf38225b5ad7ef6ee8b..b60f617585f82884ff77d0dafa18967d5bc24edb 100644 (file)
--- a/src/openpower/test/fmv_fcvt/fmv_fcvt.py
+++ b/src/openpower/test/fmv_fcvt/fmv_fcvt.py
@@ -101,7 +101,7 @@ class FMvFCvtCases(TestAccumulatorBase):
         with self.subTest(inp=inp.hex(), inp_bits=hex(inp_bits),
                           test_title=test_title,
                           signed=signed, _32bit=_32bit, CVM=CVM, RN=RN, VE=VE):
-            lst = [f"fcvttgo. 3,0,{CVM},{IT}"]
+            lst = [f"cffpro. 3,0,{CVM},{IT}"]
             gprs = [0] * 32
             fprs = [0] * 32
             fprs[0] = inp_bits
@@ -452,8 +452,8 @@ class FMvFCvtCases(TestAccumulatorBase):
 
     @staticmethod
     @functools.lru_cache(maxsize=None)
-    def _fcvtfg_fpscr(RN, set_XX, FR, FPRF, fpscr_unmodified):
-        """ cached FPSCR computation for fcvtfg_one since that part is slow """
+    def _ctfpr_fpscr(RN, set_XX, FR, FPRF, fpscr_unmodified):
+        """ cached FPSCR computation for ctfpr_one since that part is slow """
         initial_fpscr = FPSCRState()
         initial_fpscr.RN = RN
         fpscr = FPSCRState(initial_fpscr)
@@ -467,7 +467,10 @@ class FMvFCvtCases(TestAccumulatorBase):
             fpscr = FPSCRState(initial_fpscr)
         return initial_fpscr, fpscr
 
-    def fcvtfg_one(self, inp, bfp32, IT, Rc, RN):
+    def ctfpr_one(self, inp, bfp32, IT, Rc, RN):
+        if (dict(inp=hex(inp), bfp32=bfp32, IT=IT, Rc=Rc, RN=RN) !=
+                {'inp': '0x80001000', 'bfp32': True, 'IT': 3, 'Rc': True, 'RN': 0}):
+            return  # FIXME: just for debugging
         inp %= 2 ** 64
         inp_width = 64 if IT & 0b10 else 32
         inp_value = inp % 2 ** inp_width
@@ -537,7 +540,7 @@ class FMvFCvtCases(TestAccumulatorBase):
         # defined to not modify FPSCR since the conversion is always exact
         fpscr_unmodified = inp_width == 32 and not bfp32
 
-        initial_fpscr, fpscr = self._fcvtfg_fpscr(
+        initial_fpscr, fpscr = self._ctfpr_fpscr(
             RN=RN, set_XX=set_XX, FR=FR, FPRF=FPRF,
             fpscr_unmodified=fpscr_unmodified)
         if Rc:
@@ -554,7 +557,7 @@ class FMvFCvtCases(TestAccumulatorBase):
         ):
             s = "s" if bfp32 else ""
             rc_str = "." if Rc else ""
-            lst = [f"fcvtfg{s}{rc_str} 0,3,{IT}"]
+            lst = [f"ctfpr{s}{rc_str} 0,3,{IT}"]
             gprs = [0] * 32
             fprs = [0] * 32
             gprs[3] = inp
@@ -566,14 +569,14 @@ class FMvFCvtCases(TestAccumulatorBase):
                 _cached_program(*lst), gprs, fpregs=fprs, expected=e,
                 initial_fpscr=int(initial_fpscr))
 
-    def fcvtfg(self, inp):
+    def ctfpr(self, inp):
         for bfp32 in (False, True):
             for IT in range(4):
                 for Rc in (False, True):
                     for RN in range(4):
-                        self.fcvtfg_one(inp, bfp32, IT, Rc, RN)
+                        self.ctfpr_one(inp, bfp32, IT, Rc, RN)
 
-    def case_fcvtfg(self):
+    def case_ctfpr(self):
         inp_values = {0}
         for sh in (0, 22, 23, 24, 31, 52, 53, 54, 63):
             for offset in range(-2, 3):
@@ -583,7 +586,7 @@ class FMvFCvtCases(TestAccumulatorBase):
                     v %= 2 ** 64
                     inp_values.add(v)
         for i in sorted(inp_values):
-            self.fcvtfg(i)
+            self.ctfpr(i)
 
     def fmv(self, gpr_bits, bfp32, Rc):
         if bfp32:
@@ -602,10 +605,10 @@ class FMvFCvtCases(TestAccumulatorBase):
                           bfp32=bfp32, Rc=Rc):
             s = "s" if bfp32 else ""
             rc_str = "." if Rc else ""
-            tg_p = _cached_program(f"fmvtg{s}{rc_str} 3, 0")
-            # fmvfg[s]. doesn't exist since Rc=1 is basically useless due to
+            tg_p = _cached_program(f"mffpr{s}{rc_str} 3, 0")
+            # mtfpr[s]. doesn't exist since Rc=1 is basically useless due to
             # fmv* not changing any FPSCR bits
-            fg_p = _cached_program(f"fmvfg{s} 0, 3")
+            fg_p = _cached_program(f"mtfpr{s} 0, 3")
             tg_gprs = [0] * 32
             fg_gprs = [0] * 32
             tg_fprs = [0] * 32
@@ -641,8 +644,8 @@ class FMvFCvtCases(TestAccumulatorBase):
 
 
 class SVP64FMvFCvtCases(TestAccumulatorBase):
-    def case_sv_fmvfg(self):
-        lst = list(SVP64Asm(["sv.fmvfg *3, *3"]))
+    def case_sv_mtfpr(self):
+        lst = list(SVP64Asm(["sv.mtfpr *3, *3"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -672,8 +675,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fmvtg(self):
-        lst = list(SVP64Asm(["sv.fmvtg *3, *3"]))
+    def case_sv_mffpr(self):
+        lst = list(SVP64Asm(["sv.mffpr *3, *3"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -703,8 +706,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fmvfgs(self):
-        lst = list(SVP64Asm(["sv.fmvfgs *3, *3"]))
+    def case_sv_mtfprs(self):
+        lst = list(SVP64Asm(["sv.mtfprs *3, *3"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -734,8 +737,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fmvtgs(self):
-        lst = list(SVP64Asm(["sv.fmvtgs *3, *3"]))
+    def case_sv_mffprs(self):
+        lst = list(SVP64Asm(["sv.mffprs *3, *3"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -765,8 +768,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fcvtfg(self):
-        lst = list(SVP64Asm(["sv.fcvtfg *3, *3, 0"]))
+    def case_sv_ctfpr(self):
+        lst = list(SVP64Asm(["sv.ctfpr *3, *3, 0"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -796,8 +799,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fcvttg_js(self):
-        lst = list(SVP64Asm(["sv.fcvttg *3, *3, 5, 0"]))
+    def case_sv_cffpr_js(self):
+        lst = list(SVP64Asm(["sv.cffpr *3, *3, 5, 0"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -828,8 +831,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fcvttg_sat(self):
-        lst = list(SVP64Asm(["sv.fcvttg *3, *3, 3, 0"]))
+    def case_sv_cffpr_sat(self):
+        lst = list(SVP64Asm(["sv.cffpr *3, *3, 3, 0"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()
@@ -860,8 +863,8 @@ class SVP64FMvFCvtCases(TestAccumulatorBase):
         self.add_case(Program(lst, False), gprs, fpregs=fprs,
                       initial_svstate=svstate, expected=e)
 
-    def case_sv_fcvtfgs(self):
-        lst = list(SVP64Asm(["sv.fcvtfgs *3, *3, 0"]))
+    def case_sv_ctfprs(self):
+        lst = list(SVP64Asm(["sv.ctfprs *3, *3, 0"]))
         gprs = [0] * 32
         fprs = [0] * 32
         svstate = SVP64State()