gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE

FORCE_TILING should disable it. It has no effect now, but that may change
soon.

Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 97673ee22509787e88d02ab23bc6e911525c23ef..259ff36800c4cede0d81bd298af8807a9d01bdfd 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -253,6 +253,8 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 
        if (is_imported)
                flags |= RADEON_SURF_IMPORTED;
+       if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
+               flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
        r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
                                      array_mode, surface);

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 3e30e95457458f1ceacd0e261301ff6ef754b5da..3027c4a8b535a0bdd423a028f043932b19d27029 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -281,6 +281,7 @@ enum radeon_micro_mode {
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
+#define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 
 struct radeon_surf_level {
     uint64_t                    offset;

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index d65dae726610df812721eca636a7bacf2087b3a5..d8ab28b36fdc3cd6a29249ce33213d5ec717de1a 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -402,7 +402,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
     * requested, because TC-compatible HTILE requires 2D tiling.
     */
    AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
-                                        !(flags & RADEON_SURF_FMASK);
+                                        !AddrSurfInfoIn.flags.fmask &&
+                                        tex->nr_samples <= 1 &&
+                                        (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
 
    /* DCC notes:
     * - If we add MSAA support, keep in mind that CB can't decompress 8bpp