Add citation
authorEddie Hung <eddie@fpgeh.com>
Wed, 27 Nov 2019 06:51:16 +0000 (22:51 -0800)
committerEddie Hung <eddie@fpgeh.com>
Wed, 27 Nov 2019 06:51:16 +0000 (22:51 -0800)
tests/arch/xilinx/dsp_fastfir.ys

index 30e74a01b1c05d008a310040e854354c3639f40a..b205d42c1f2a73a1bdbf92a530fdbf44748b75f3 100644 (file)
@@ -1,4 +1,5 @@
 read_verilog <<EOT
+// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v
 module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
   wire [30:0] _00_;
   wire [23:0] _01_;