arch-x86: Make CPUID vendor string a param

Modern libraries such as ROCm, MPI, and libnuma use files in Linux'
sysfs to determine the system topology such as number of CPUs, cache
size, cache associativity, etc. If Linux does not recognize the vendor
string returned by CPUID in x86 it will do a generic initialization
which does not include creating these files. In the case of ROCm
(specifically ROCt) this causes failures when getting device properties.

This can be solved by setting the vendor string to, for example,
AuthenticAMD (as qemu does) so that Linux will create the relevant sysfs
files. Unfortunately, simply changing the string in cpuid.cc to
AuthenticAMD causes simulation slowdown and may not be desirable to all
users. This change creates a parameter, defaulting to M5 Simulator as it
currently is, which can be set in python configuration files to change
the vendor string. Example of how to configure this is:

for i in range(len(self.cpus)):
    for j in range(len(self.cpus[i].isa)):
        self.cpus[i].isa[j].vendor_string = "AuthenticAMD"

Change-Id: I8de26d5a145867fa23518718a799dd96b5b9bffa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36156
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
index d73d99a0416fdea8a6b4d33290d7bbed5f8785a9..1503f5fa68377508a4c438d2c4a48f3e8333fedd 100644 (file)
--- a/src/arch/x86/X86ISA.py
+++ b/src/arch/x86/X86ISA.py
@@ -34,8 +34,12 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.BaseISA import BaseISA
+from m5.params import *
 
 class X86ISA(BaseISA):
     type = 'X86ISA'
     cxx_class = 'X86ISA::ISA'
     cxx_header = "arch/x86/isa.hh"
+
+    vendor_string = Param.String("M5 Simulator",
+                                 "Vendor string for CPUID instruction")

diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 64d4544f8c1413e25a6e6802f9710796677231b5..8c9f29cef9c42cecc0f71d7714cfb0d33aad25f5 100644 (file)
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -28,6 +28,7 @@
 
 #include "arch/x86/cpuid.hh"
 
+#include "arch/x86/isa.hh"
 #include "base/bitfield.hh"
 #include "cpu/thread_context.hh"
 
@@ -67,8 +68,6 @@ namespace X86ISA {
         NumExtendedCpuidFuncs
     };
 
-    static const int vendorStringSize = 13;
-    static const char vendorString[vendorStringSize] = "M5 Simulator";
     static const int nameStringSize = 48;
     static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
 
@@ -93,12 +92,15 @@ namespace X86ISA {
             // The extended functions
             switch (funcNum) {
               case VendorAndLargestExtFunc:
-                assert(vendorStringSize >= 12);
-                result = CpuidResult(
-                        0x80000000 + NumExtendedCpuidFuncs - 1,
-                        stringToRegister(vendorString),
-                        stringToRegister(vendorString + 4),
-                        stringToRegister(vendorString + 8));
+                {
+                  ISA *isa = dynamic_cast<ISA *>(tc->getIsaPtr());
+                  const char *vendor_string = isa->getVendorString().c_str();
+                  result = CpuidResult(
+                          0x80000000 + NumExtendedCpuidFuncs - 1,
+                          stringToRegister(vendor_string),
+                          stringToRegister(vendor_string + 4),
+                          stringToRegister(vendor_string + 8));
+                }
                 break;
               case FamilyModelSteppingBrandFeatures:
                 result = CpuidResult(0x00020f51, 0x00000405,
@@ -151,12 +153,15 @@ namespace X86ISA {
             // The standard functions
             switch (funcNum) {
               case VendorAndLargestStdFunc:
-                assert(vendorStringSize >= 12);
-                result = CpuidResult(
-                        NumStandardCpuidFuncs - 1,
-                        stringToRegister(vendorString),
-                        stringToRegister(vendorString + 4),
-                        stringToRegister(vendorString + 8));
+                {
+                  ISA *isa = dynamic_cast<ISA *>(tc->getIsaPtr());
+                  const char *vendor_string = isa->getVendorString().c_str();
+                  result = CpuidResult(
+                          NumExtendedCpuidFuncs - 1,
+                          stringToRegister(vendor_string),
+                          stringToRegister(vendor_string + 4),
+                          stringToRegister(vendor_string + 8));
+                }
                 break;
               case FamilyModelStepping:
                 result = CpuidResult(0x00020f51, 0x00000805,

diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index e4e526e0964b942ea7f8267422e1bce72c8891e1..2465a19d2ae1ad7cda553f25f445abcef204ca18 100644 (file)
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -130,8 +130,10 @@ ISA::clear()
     regVal[MISCREG_APIC_BASE] = lApicBase;
 }
 
-ISA::ISA(const Params &p) : BaseISA(p)
+ISA::ISA(const X86ISAParams &p) : BaseISA(p), vendorString(p.vendor_string)
 {
+    fatal_if(vendorString.size() != 12,
+             "CPUID vendor string must be 12 characters\n");
     clear();
 }
 
@@ -434,4 +436,10 @@ ISA::setThreadContext(ThreadContext *_tc)
     tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
 }
 
+std::string
+ISA::getVendorString() const
+{
+    return vendorString;
+}
+
 }

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 3df7cce925096999b1fa14546b5a3b0ab4185a07..2cbce6e891f48e4d82c45e9df8cf5ec04b327cd5 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -108,6 +108,11 @@ namespace X86ISA
         void unserialize(CheckpointIn &cp) override;
 
         void setThreadContext(ThreadContext *_tc) override;
+
+        std::string getVendorString() const;
+
+      private:
+        std::string vendorString;
     };
 }